POLISHING PAD FOR SEMICONDUCTOR HYBRID BONDING AND PREPARATION METHOD OF SEMICONDUCTOR DEVICE USING THE SAME

Abstract

According to embodiments of the present invention, there are provided a polishing pad and a process for preparing a semiconductor device using the polishing pad. The polishing pad comprises a polishing layer having a polishing selectivity within a predetermined range depending on the coefficient of thermal expansion of an object to be polished. The dishing of the semiconductor substrate is controlled during the polishing process, whereby surface defects and bonding failures of semiconductor devices can be reduced.

Claims

1. A polishing pad, which comprises a polishing layer, wherein the dishing value is 0.5 nm to 3.5 nm, and wherein when an object to be polished comprising a first region having a coefficient of thermal expansion of 1.010.sup.7 mm/mm C. to 3.510.sup.6 mm/mm C. and a second region having a coefficient of thermal expansion of 4.010.sup.6 mm/mm C. to 3.010.sup.5 mm/mm C. is polished for 10 seconds with the polishing pad under the conditions of a rotation speed of the polishing pad of 93 rpm, a rotation speed of the object to be polished of 87 rpm, and a polishing load of 5.0 psi, while a ceria slurry (ACS-580, KC Tech) is sprayed at a rate of 150 ml/minute, the dishing value is the difference in thickness change (nm) between the first region and the second region.

2. The polishing pad of claim 1, wherein the first region comprises a dielectric material, and the second region comprises a metal.

3. The polishing pad of claim 1, wherein the first region is a silicon oxide (SiO.sub.2) film, and the second region is a copper (Cu) film.

4. The polishing pad of claim 1, wherein the polishing layer comprises a plurality of pores.

5. The polishing pad of claim 4, wherein the average diameter (Dn.sub.50) of the plurality of pores is 18 m to 30 m.

6. The polishing pad of claim 4, wherein the plurality of pores comprise first pores having a diameter of 16.9 m or less and second pores having a diameter of 27.4 m or more.

7. The polishing pad of claim 6, wherein the total volume of the first pores is 10% by volume or less, and the total volume of the second pores is 10% by volume or less, based on the total volume of the plurality of pores.

8. The polishing pad of claim 4, wherein the polishing layer comprises a cured product of a raw material mixture comprising a urethane-based prepolymer, a solid phase foaming agent, and a curing agent, and the plurality of pores are derived from the solid phase foaming agent.

9. A process for preparing a semiconductor device, which comprises: mounting the polishing pad of claim 1 on a platen; mounting a semiconductor substrate on a head such that the surface, to be polished, of the semiconductor substrate is brought into contact with the polishing surface of the polishing pad; and rotating the polishing pad and the semiconductor substrate relative to each other to polish the surface, to be polished, of the semiconductor substrate.

10. A process for preparing a semiconductor device, which comprises: polishing the upper side of a first semiconductor substrate and the lower side of a second semiconductor substrate using the polishing pad of claim 1; attaching the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate so as to face each other; and thermally treating the first semiconductor substrate and the second semiconductor substrate.

11. The process for preparing a semiconductor device according to claim 10, wherein the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate each comprise a first region and a second region.

12. The process for preparing a semiconductor device according to claim 11, wherein the attachment step comprises bring the first region of the first semiconductor substrate and the first region of the second semiconductor substrate into contact with each other.

13. The process for preparing a semiconductor device according to claim 11, wherein in the attachment step, at least a portion of the second region of the first semiconductor substrate is physically separated from the second region of the second semiconductor substrate.

14. The process for preparing a semiconductor device according to claim 11, wherein in the thermal treatment step, the second region of the first semiconductor substrate and the second region of the second semiconductor substrate expand to be integrated.

15. The process for preparing a semiconductor device according to claim 10, wherein the thermal treatment step comprises a first thermal treatment step carried out at a temperature of 200 C. or lower and a second thermal treatment step carried out at a temperature of 300 C. or higher.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIGS. 1a and 1b are schematic drawings for explaining the dishing value of the present invention.

[0019] FIGS. 2a to 2c are drawings for explaining the bonding defects of a semiconductor substrate with respect to dishing values.

[0020] FIGS. 3a to 3c are drawings for explaining the bonding defects of a semiconductor substrate with respect to dishing values.

[0021] FIG. 4 is a schematic cross-sectional view showing a polishing pad according to an embodiment of the present invention.

[0022] FIG. 5 is a schematic process flow diagram for explaining a process for preparing a semiconductor device according to an embodiment of the present invention.

[0023] FIG. 6 is a schematic process flow diagram for explaining a process for preparing a semiconductor device according to another embodiment of the present invention.

[0024] FIG. 7 is a cross-sectional image obtained by a 3D CT-scan of the polishing pad of Example 1.

BEST MODE FOR CARRYING OUT THE INVENTION

[0025] Hereinafter, the present invention will be described in detail with reference to various examples and embodiments. The embodiments are not limited to what has been disclosed below. The embodiments may be modified into various forms as long as the gist of the invention is not altered.

[0026] In this specification, terms referring to the respective components are used to distinguish them from each other and are not intended to limit the scope of the embodiment. In addition, in the present specification, a singular expression is interpreted to cover a plural number as well unless otherwise specified in the context.

[0027] Throughout the present specification, when a part is referred to as comprising an element, it is understood that other elements may be comprised, rather than other elements are excluded, unless specifically stated otherwise.

[0028] In the present specification, when one component is described to be formed on/under another component or connected or coupled to each other, it covers the cases where these components are directly or indirectly formed, connected, or coupled through another component. In addition, it should be understood that the criterion for the terms on and under of each component may vary depending on the direction in which the object is observed.

[0029] All numerical ranges related to the physical properties, dimensions, and the like of a component used herein are to be understood as being modified by the term about, unless otherwise indicated.

[0030] In the numerical range that limits the size of components, physical properties, and the like described in the present specification, when a numerical range limited with the upper limit only and a numerical range limited with the lower limit only are separately exemplified, it should be understood that a numerical range combining these upper and lower limits is also encompassed in the exemplary scope.

[0031] The terms first, second, and the like are used herein to describe various elements, and the elements should not be limited by the terms. But the components should not be limited by the terms. The terms are used for the purpose of distinguishing one element from another.

[0032] In the drawings of the present specification, the shape, size, ratio, and the like of each component are exaggerated, omitted, or schematically depicted for convenience of explanation. The embodiments of the present invention are not limited to the shape, size, ratio, and the like of each component illustrated in the drawings.

Polishing Pad

[0033] The polishing pad according to embodiments of the present invention comprises a polishing layer, wherein the dishing value may be 0.5 nm to 3.5 nm.

[0034] When the surface of an object to be polished that comprises a first region having a first coefficient of thermal expansion and a second region having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion is polished for 10 seconds with the polishing pad, the dishing value is the difference in thickness change (nm) between the first region and the second region.

[0035] For example, the dishing value may be expressed by the following Equation 1.

[00001]$\begin{array}{cc}\mathrm{Dishing}\mathrm{value}\left(\mathrm{nm}\right)=\mathrm{thickness}\mathrm{change}\mathrm{in}\mathrm{the}\mathrm{second}\mathrm{region}\left(\mathrm{nm}\right)-\mathrm{thickness}\mathrm{change}\mathrm{in}\mathrm{the}\mathrm{first}\mathrm{region}\left(\mathrm{nm}\right)& \left[\mathrm{Equation}1\right]\end{array}$

[0036] The above polishing process may be carried out for 10 seconds under the conditions of a rotation speed of the polishing pad of 93 rpm, a rotation speed of the object to be polished of 87 rpm, and a polishing load of 5.0 psi, while a ceria slurry is sprayed.

[0037] The ceria slurry may be ACS-580 (KC Tech), and the spraying speed of the ceria slurry may be 150 ml/minute. In an embodiment, the thickness change may be measured using a CMP system (POLI-400 LM, G&P Technology). The measurement temperature may be 20 C., but it is not limited thereto.

[0038] In the above polishing process, the first region and the second region may be exposed toward the polishing pad on the surface (surface to be polished) of the object to be polished. For example, the dishing value may be measured by polishing the surface to be polished using the polishing pad while the upper side of the first region and the upper side of the second region are positioned at the same height or level as the surface, to be polished, of the object to be polished.

[0039] Thickness change may refer to the difference in thickness of the most polished portion of the polished region after polishing relative to the thickness of the region to be polished before polishing. For example, the thickness change may refer to the reduced thickness in the central portion when the central portion of the region to be removed by the polishing process is polished more than the edge. It may refer to the reduced thickness at the edge when the edge of the region to be removed is polished more than the central portion.

[0040] In an embodiment, when the first region and the second region have the same thickness before the polishing process, the difference in thickness change (dishing value) between the first region and the second region may be calculated as the difference between the lowest thickness of the first region and the lowest thickness of the second region measured after the polishing process.

[0041] Dishing refers to a phenomenon in which, after a CMP process on a semiconductor substrate, the upper side of a metal layer on the semiconductor substrate is not located at the same level as the upper side of a dielectric material such as an oxide or nitride, whereby a concave or convex recess is formed. The dishing may be expressed numerically through the dissing value, so that the degree of dishing due to a CMP process, for example, the degree of deviation from flatness, may be quantitatively evaluated.

[0042] FIGS. 1a and 1b are schematic drawings for explaining the dishing value. Specifically, FIG. 1a is a schematic cross-sectional view of an object to be polished before a polishing process, and FIG. 1b is a schematic cross-sectional view of the polished object after a polishing process.

[0043] Referring to FIG. 1a, the object to be polished (100) comprises a base substrate (105) and may comprise a first region (110) having a first coefficient of thermal expansion and a second region (120) having a second coefficient of thermal expansion on the surface of the base substrate (105). The polishing surface (205) of the polishing pad (200) is brought into contact with the surface of the object to be polished (100) and rotated relative thereto, whereby the surface of the object (100) may be polished.

[0044] Referring to FIG. 1b, the object to be polished (100) may be polished by a polishing process to reduce its thickness. The line (BP) shown as a dotted line in FIG. 1b indicates the height of the object to be polished (100) before the polishing process. Due to the difference in polishing rates in the first region (110) and the second region (120), the upper side of the first region (110) and the upper side of the second region (120) may be located at different levels after the polishing process, and a recess (125) may be formed in the second region (120). In FIG. 1b, the second region (120) is depicted as having a recess (125) in a concave shape, but it is not limited thereto. A recess (125) in a convex shape may be formed depending on the properties of the polishing pad, the conditions of the polishing process, the materials or properties of the first region and the second region, and the like.

[0045] The dishing value may be calculated by the difference (Dv) between the reduced thickness in the second region (120) and the reduced thickness in the first region (110). The reduced thickness refers to the thickness change in the most polished part in each region.

[0046] As the dishing value is adjusted to the above range by the polishing pad, surface defects such as scratches and chatter marks appearing on the surface of an object to be polished (e.g., a semiconductor substrate) can be suppressed. In addition, the defect rate in the bonding process of semiconductor substrates and the packaging process of semiconductor devices can be reduced.

[0047] For example, in the process for preparing a semiconductor device, a semiconductor substrate such as a wafer and die may comprise different materials with different properties on the same surface. Accordingly, hybrid bonding may be used to join two or more semiconductor substrates to each other. In hybrid bonding, materials with similar properties on each semiconductor substrate may be bonded to each other. Specifically, a metallic material (e.g., circuit wiring) of an upper substrate and a metallic material of a lower substrate may be bonded to each other, and a dielectric material (e.g., an insulation film) of an upper substrate and a dielectric material of a lower substrate may be bonded to each other.

[0048] In an embodiment, in hybrid bonding, the semiconductor substrates attached to each other may be bonded as a whole through thermal treatment. For example, the metallic material and dielectric material provided on the surfaces of the respective upper and lower substrates may be connected or integrated by expanding through thermal treatment. In such a case, since the metallic material and the inorganic material have different coefficients of thermal expansion (CTE), lifting or bonding failure may occur due to the differences in the coefficients of thermal expansion in the respective regions at the bonding interface. According to embodiments of the present invention, as the dishing value of the polishing pad is adjusted to the above range, even if a semiconductor substrate comprises different regions at the bonding interface, bonding failure due to a difference in the coefficients of thermal expansion between the regions can be prevented, and the adhesion between the semiconductor substrates and the connection quality between the circuit wirings can be enhanced, so that the performance of the semiconductor device can be enhanced.

[0049] FIGS. 2a to 2c are drawings for explaining the bonding defects of a semiconductor substrate when the dishing value is less than 0.5 nm. Specifically, FIG. 2a is a schematic cross-sectional view of semiconductor substrates after a polishing process, FIG. 2b is a schematic cross-sectional view of semiconductor substrates after an attachment process, and FIG. 2c is a schematic cross-sectional view of semiconductor substrates after a thermal treatment process.

[0050] Referring to FIGS. 2a to 2c, when the dishing value is less than 0.5 nm, a recess (125) may not be sufficiently formed in the region (120) having a high coefficient of thermal expansion (e.g., a second coefficient of thermal expansion), for example, a metallic region, on the surface of the semiconductor substrate during the polishing process (see FIG. 2a). As a result, when the upper substrate (UB) and the lower substrate (LB) are bonded, a sufficient gap (130) may not be secured between the regions (120) having a high coefficient of thermal expansion to accommodate the expansion due to thermal treatment (see FIG. 2b). Accordingly, during the thermal treatment process, while the regions (120) with a high coefficient of thermal expansion repel each other due to differences in the coefficients of thermal expansion, voids are formed between the regions with a low coefficient of thermal expansion (e.g., a first coefficient of thermal expansion), which may cause lifting between the substrates or damage thereto (see FIG. 2c).

[0051] For example, the dishing value may be less than 0.5 nm when the polishing rate for the region having a second coefficient of thermal expansion (e.g., a metal or the like) is substantially similar to, or lower than, the polishing rate for the region having a first coefficient of thermal expansion (e.g., a dielectric material or the like).

[0052] FIGS. 3a to 3c are drawings for explaining the bonding defects of a semiconductor substrate when the dishing value exceeds 3.5 nm. Specifically, FIG. 3a is a schematic cross-sectional view of semiconductor substrates after a polishing process, FIG. 3b is a schematic cross-sectional view of semiconductor substrates after an attachment process, and FIG. 3c is a schematic cross-sectional view of semiconductor substrates after a thermal treatment process.

[0053] Referring to FIGS. 3a to 3c, when the dishing value exceeds 3.5 nm, a relatively deep recess (125) may be formed in the region (120) having a high coefficient of thermal expansion on the surface of the semiconductor substrate after polishing (see FIG. 3a). Accordingly, when the semiconductor substrates are bonded to each other, an excessively large gap (130) may be formed between the semiconductor substrates in the region (120) having a high coefficient of thermal expansion (see FIG. 3b). In such a case, even if the regions (120) having a high coefficient of thermal expansion expand due to thermal treatment, they may not be brought into contact with each other. As a result, poor connection between the semiconductor substrates may occur (see FIG. 3c).

[0054] For example, the dishing value may be less than 0.5 nm when the polishing rate for the region having a second coefficient of thermal expansion (e.g., a metal or the like) is substantially similar to, or lower than, the polishing rate for the region having a first coefficient of thermal expansion (e.g., a dielectric material or the like).

[0055] The first coefficient of thermal expansion may be 1.010.sup.7 mm/mm C. to 3.510.sup.6 mm/mm C., and the second coefficient of thermal expansion may be 4.010.sup.6 mm/mm C. to 3.010.sup.5 mm/mm C. As the dishing value for the regions having coefficients of thermal expansion within the above ranges is adjusted within the above range, the expanded volume of the respective regions can appropriately fill the gap between the semiconductor substrates during the thermal treatment process. Accordingly, the bonding stability and connectivity between the semiconductor substrates can be further enhanced.

[0056] For example, the first coefficient of thermal expansion may be 3.510.sup.6 mm/mm C. or less, 3.010.sup.6 mm/mm C. or less, 1.010.sup.6 mm/mm C. or less, 9.010.sup.7 mm/mm C. or less, 8.010.sup.7 mm/mm C. or less, or 7.010.sup.7 mm/mm C. or less. For example, the first coefficient of thermal expansion may be 1.010.sup.7 mm/mm C. or more, 1.510.sup.7 mm/mm C. or more, 2.010.sup.7 mm/mm C. or more, 3.010.sup.7 mm/mm C. or more, or 4.010.sup.7 mm/mm C. or more.

[0057] In an embodiment, the first coefficient of thermal expansion may be 1.510.sup.7 mm/mm C. to 3.010.sup.6 mm/mm C., 2.010.sup.7 mm/mm C. to 1.010.sup.6 mm/mm C., 3.010.sup.7 mm/mm C. to 9.010.sup.7 mm/mm C., or 4.010.sup.7 mm/mm C. to 7.010.sup.7 mm/mm C.

[0058] In some embodiments, the region having the first coefficient of thermal expansion may comprise a dielectric material. For example, the dielectric material may comprise an oxide, a nitride, or the like. More specifically, it may comprise silicon oxide (SiO.sub.2), silicon nitride (SiNx), or the like.

[0059] For example, the second coefficient of thermal expansion may be 4.010.sup.6 mm/mm C. or more, 5.010.sup.6 mm/mm C. or more, 1.010.sup.5 mm/mm C. or more, 1.510.sup.5 mm/mm C. or more, or 1.610.sup.5 mm/mm C. or more. For example, the second coefficient of thermal expansion may be 3.010.sup.5 mm/mm C. or less, 2.810.sup.5 mm/mm C. or less, 2.510.sup.5 mm/mm C. or less, 2.410.sup.5 mm/mm C. or less, 2.210.sup.5 mm/mm C. or less, or 2.110.sup.5 mm/mm C. or less.

[0060] In an embodiment, the second coefficient of thermal expansion may be 5.010.sup.6 mm/mm C. to 2.810.sup.5 mm/mm C., 1.010.sup.5 mm/mm C. to 2.510.sup.5 mm/mm C., 1.510.sup.5 mm/mm C. to 2.410.sup.5 mm/mm C., or 1.610.sup.5 mm/mm C. to 2.110.sup.5 mm/mm C.

[0061] In some embodiments, the region having the second coefficient of thermal expansion may comprise a metal. For example, the metal may comprise copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), or the like.

[0062] The first coefficient of thermal expansion and the second coefficient of thermal expansion may be measured at a heating rate of 10 C./minute using a thermomechanical analyzer (TMA). Specifically, the coefficient of thermal expansion may be measured using the penetration method under the conditions of a heating rate of 10 C./minute, a load of 50 g, and a pin wire of 0.5 mm.

[0063] In an embodiment, the difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion may be 1.010.sup.6 mm/mm C. or more, 5.010.sup.6 mm/mm C. or more, 9.010.sup.6 mm/mm C. or more, 1.010.sup.5 mm/mm C. or more, 1.310.sup.5 mm/mm C. or more, or 1.510.sup.5 mm/mm C. or more, and may be 2.710.sup.5 mm/mm C. or less, 2.510.sup.5 mm/mm C. or less, 2.210.sup.5 mm/mm C. or less, 2.010.sup.5 mm/mm C. or less, or 1.810.sup.5 mm/mm C. or less.

[0064] In some embodiments, the dishing value may be 0.5 nm or more, 1.0 nm or more, 1.5 nm or more, 1.8 nm or more, 2.0 nm or more, or 2.1 nm or more. As a result, surface roughness can be reduced in the region having a low coefficient of thermal expansion, and surface flatness can be further improved. In addition, a sufficient recess space is secured in the region having a high coefficient of thermal expansion so that the volume expanded by thermal treatment can be readily accommodated. Accordingly, the bonding stability between the semiconductor substrates can be further enhanced.

[0065] In some embodiments, the dishing value may be 3.5 nm or less, 3.3 nm or less, 3.0 nm or less, 2.9 nm or less, 2.7 nm or less, or 2.5 nm or less. As a result, while erosion is prevented during the polishing process, an appropriate upper and lower gap is formed between the regions having a high coefficient of thermal expansion during the bonding process of the substrates, so that contact can be enhanced during the thermal treatment process. Accordingly, poor connection between circuit wirings of the semiconductor substrates can be prevented, and bonding stability can be further improved.

[0066] In an embodiment, the dishing value may be 0.5 nm to 3.5 nm, 1.0 nm to 3.5 nm, 1.0 nm to 3.3 nm, 1.0 nm to 3.0 nm, 1.5 nm to 3.0 nm, 1.8 nm to 3.0 nm, 1.8 nm to 2.9 nm, 2.0 nm to 2.7 nm, 2.0 nm to 2.5 nm, or 2.1 nm to 2.5 nm.

[0067] The polishing layer may have a porous structure comprising a plurality of pores. In some embodiments, the average diameter (Dn.sub.50) of the plurality of pores may be 18 m to 30 m.

[0068] The average diameter (Dn.sub.50) of the pores may be measured through a 3D CT-scan. For example, based on the unit area of a polishing pad (1 cm.sup.2), it is possible to measure the pores inside the polishing layer by a 3D CT-scan, and the CT data analysis and visualization software called Volume Graphics may be used to calculate the diameter, area, volume, and number of the pores. For example, the volume of a pore with a radius of r may be calculated as 4r.sup.3/3. The average diameter (Dp.sub.50) may be defined as the diameter of the pore at a volume fraction of 50% in a volume distribution obtained by accumulating the pores in order of increasing diameter.

[0069] The surface condition of the polishing pad, the flowability of a polishing slurry, and the polishing efficiency may vary depending on the average diameter of the pores. For example, as the average diameter of the pores decreases, the depth, width, and roughness of the grooves formed on the surface of the polishing layer decrease, and the spacing and number of the grooves increase, whereby the real contact area between the polishing pad and the object to be polished may increase. As the average diameter of the plurality of pores contained in the polishing layer is controlled within the above range, the flowability of a polishing slurry is secured, thereby suppressing the occurrence of surface defects, and the pressure applied to the object to be polished is dispersed, so that the polishing rate and surface flatness for each object to be polished can be more readily controlled within a desired range.

[0070] In an embodiment, the average diameter (Dn.sub.50) of the plurality of pores may be 18 m to 29 m, 18 m to 27 m, 18 m to 26 m, 19 m to 26 m, 19 m to 25 m, 20 m to 25 m, 21 m to 25 m, 21 m to 24 m, 22 m to 24 m, or 22 m to 23 m.

[0071] Dn.sub.10 of the plurality of pores may be 5 m to 21 m, 10 m to 20 m, 15 m to 20 m, 15 m to 19 m, 15 m to 18 m, or 16 m to 18 m. Dn.sub.10 may be defined as the diameter of the pore at a volume fraction of 10% in a volume distribution obtained by accumulating the pores in order of increasing diameter.

[0072] Dn.sub.90 of the plurality of pores may be 20 m to 45 m, 23 m to 45 m, 23 m to 40 m, 25 m to 40 m, 27 m to 40 m, 27 m to 35 m, or 27 m to 30 m. Dn.sub.90 may be defined as the diameter of the pore at a volume fraction of 90% in a volume distribution obtained by accumulating the pores in order of increasing diameter.

[0073] As the size and distribution of the pores are controlled in the range of Dn.sub.10, Dn.sub.50, and Dn.sub.90 of the plurality of pores, the polishing characteristics for, for example, a metal film and a dielectric film can be adjusted to a desired degree, and the dishing value in the above range can be more readily provided.

[0074] In some embodiments, the plurality of pores may comprise first pores having a diameter of 16.9 m or less, second pores having a diameter of 27.4 m or more, and third pores having a diameter of greater than 16.9 m and less than 27.4 m. The total volume of the first pores may be 10% by volume or less, and the total volume of the second pores may be 10% by volume or less, based on the total volume of the plurality of pores. The volume of the first pores and the volume of the second pores may be obtained from the volume distribution of the pores described above. Within the above range, the formation of pores having excessively small or large diameters relative to the average diameter is controlled, and the plurality of pores have relatively uniform sizes, whereby the polishing degree for each region can be controlled to be constant.

[0075] In an embodiment, the total volume of the first pores may be 5% by volume to 10% by volume, and the total volume of the second pores may be 5% by volume to 10% by volume, based on the total volume of the plurality of pores. Within the above range, as the pores are more uniformly distributed within the polishing layer, the polishing efficiency can be further enhanced, and the dishing value can be more readily controlled.

[0076] The polishing layer of the polishing pad may comprise a resin. For example, the polishing layer may comprise a urethane-based resin.

[0077] In an embodiment, the polishing layer may comprise a cured product of a composition comprising a urethane-based prepolymer, a curing agent, and a foaming agent. Pores can be formed within the polishing layer by the foaming agent.

[0078] As the composition and properties of the polishing layer, and the shape, size, distribution, and content of pores are controlled, the polishing selectivity for the different materials having different coefficients of thermal expansion, such as metals and dielectric materials, can be adjusted. As a result, the surface flatness and recess of the polished object after a CMP process can be appropriately adjusted, so that the dishing value can be readily controlled within the above range.

[0079] FIG. 4 is a schematic cross-sectional view showing a polishing pad according to embodiments of the present invention.

[0080] Referring to FIG. 4, the polishing pad (10) may comprise a polishing layer (12) as a top pad layer and may further comprise a support layer (16) as a sub pad layer under the polishing layer (12).

[0081] The polishing layer (12) may have a thickness of 0.5 mm to 5 mm. For example, the thickness of the polishing layer (12) may be 0.8 mm to 4.0 mm, 1.0 mm to 3.0 mm, 1.5 mm to 2.5 mm, 1.7 mm to 2.3 mm, or 2.0 mm to 2.2 mm. As the thickness of the polishing layer (12) increases, the size variation of the pores contained in the polishing layer (12) between the upper and lower regions may increase. As the thickness thereof decreases, the physical properties of the polishing layer (12) may deteriorate. When the thickness of the polishing layer (12) satisfies the above range, the physical properties of the polishing pad (10) for a CMP process can be secured while the diameter variation of the pores is minimized.

[0082] The support layer (16) is positioned under the polishing layer (12) to stably support the polishing layer (12) while absorbing and dispersing the impact applied to the polishing layer (12). The support layer (16) may be prepared using a nonwoven fabric, suede, or a porous pad.

[0083] The thickness of the support layer (16) may be, for example, 0.5 mm to 4 mm, 0.6 mm to 3.5 mm, 0.8 mm to 3 mm, or 1 mm to 2 mm. Within the above range, the polishing pad (10) can be made lighter while the support layer (16) can support the polishing layer (12) more stably.

[0084] In some embodiments, the polishing pad (10) may further comprise an adhesive layer (14) between the polishing layer (12) and the support layer (16). The adhesive layer (14) may be in contact with the lower side of the polishing layer (12) and the upper side of the support layer (16) to bond the polishing layer (12) and the support layer (16). Further, the adhesive layer (14) may also serve as a barrier layer to prevent a polishing slurry supplied to the polishing layer (12) from leaking into the support layer (16). In an embodiment, the adhesive layer (14) may be formed using a hot melt adhesive composition.

[0085] The hot melt adhesive composition may comprise a hot melt adhesive commonly known. In an embodiment, the hot melt adhesive may comprise a polyurethane resin, a polyester resin, an ethylene-vinyl acetate resin, a polyamide resin, and/or a polyolefin resin. They may be used alone or in combination of two or more.

[0086] The thickness of the adhesive layer (14) may be, for example, 5 m to 30 m, 10 m to 30 m, 20 m to 27 m, or 23 m to 25 m. Within the above range, the bonding strength between the polishing layer (12) and the support layer (16) can be further enhanced, and the polishing pad (10) can be made lighter.

Process for Preparing a Polishing Pad

[0087] In the process for preparing a polishing pad according to embodiments of the present invention, a urethane-based prepolymer, a curing agent, and a foaming agent may be mixed to prepare a raw material mixture.

[0088] A prepolymer generally refers to a polymer having a relatively low molecular weight wherein the degree of polymerization is adjusted to an intermediate level for the sake of conveniently molding a product in the process of producing the same. A prepolymer may be molded by itself or after a reaction with another polymerizable compound. For example, a prepolymer may be prepared by reacting an isocyanate compound with a polyol.

[0089] The urethane-based prepolymer may be prepared by reacting an isocyanate compound with a polyol.

[0090] For example, the isocyanate compound may comprise at least one compound selected from the group consisting of toluene diisocyanate (TDI), naphthalene-1,5-diisocyanate, p-phenylene diisocyanate, tolidine diisocyanate, 4,4-diphenyl methane diisocyanate, hexamethylene diisocyanate, dicyclohexylmethane diisocyanate, and isophorone diisocyanate.

[0091] For example, the polyol may comprise at least one compound selected from the group consisting of a polyether polyol, a polyester polyol, a polycarbonate polyol, and an acryl polyol.

[0092] In an embodiment, the polyol may have a weight average molecular weight (Mw) of 300 g/mole to 3,000 g/mole.

[0093] In an embodiment, the urethane-based prepolymer may be a polymer prepared by reacting an isocyanate compound comprising toluene diisocyanate and a polyol comprising polytetramethylene ether glycol.

[0094] In some embodiments, the urethane-based prepolymer may have a weight average molecular weight of 500 g/mole to 3,000 g/mole. Specifically, the urethane-based prepolymer may have a weight average molecular weight of 600 g/mole to 2,000 g/mole or 800 g/mole to 1,000 g/mole.

[0095] In an embodiment, the urethane-based prepolymer may have an isocyanate terminal group (terminal NCO) content (NCO %) of 5% by weight to 15% by weight based on the total weight of the urethane-based prepolymer. For example, the terminal NCO content (NCO %) of the urethane-based prepolymer may be 6% by weight to 13% by weight, 7% by weight to 12% by weight, 7.5% by weight to 11% by weight, or 8% by weight to 10% by weight. As the weight average molecular weight and NCO % of the urethane-based prepolymer each satisfy the above ranges, the polishing rate for an object to be polished in a CMP process can be adjusted to a desired range, and the dishing value of the polishing pad can be appropriately adjusted.

[0096] The foaming agent may comprise a solid phase foaming agent. For example, the plurality of pores in the polishing pad may be derived from a solid phase foaming agent.

[0097] When a solid phase foaming agent is used, the shape, size, content, and distribution of pores can be controlled more precisely than when a liquid phase or gas phase foaming agent is used. For example, the shape, size, content, and distribution of pores may vary depending on the particle size, distribution, shape, constituents, and elemental composition of the solid phase foaming agent. In addition, since the solid phase foaming agent has an outer shell and a void, the shape of the micropores contained within the polishing layer can be maintained even during a CMP process, which can further improve the polishing performance.

[0098] In some embodiments, the solid phase foaming agent may be purified by a purification system. As a result, the solid phase foaming agent can have uniform density, average particle size, solvent resistance, thermal resistance, and the like.

[0099] In an embodiment, the solid phase foaming agent may have an average particle diameter (D.sub.50) of 1 m to 20 m. The average particle diameter (D.sub.50) may be defined as the particle diameter at a volume fraction of 50% in a volume particle distribution obtained by accumulating the particles in order of increasing particle diameter. For example, the D.sub.50 of the solid phase foaming agent may be 1 m to 15 m, 5 m to 15 m, 5 m to 10 m, or 6 m to 9 m. For example, the purification system can filter out particles having excessively small or large particle sizes, so that the average particle size of the solid phase foaming agent can be controlled within the above range.

[0100] When the D.sub.50 of the solid phase foaming agent is within the above range, the polishing rate and flatness can be more readily controlled within the desired ranges. For example, the size, distribution, shape, or content of pores in the polishing layer can be controlled by the D.sub.50 of the solid phase foaming agent. It can also have an impact on the dishing value of an object to be polished.

[0101] In some embodiments, the solid phase foaming agent may comprise thermally expanded particles. When the solid phase foaming agent comprises thermally expanded particles, the D.sub.50 of the solid phase foaming agent may refer to the average particle diameter in a thermally expanded state. The thermally expanded particles may be obtained by thermally expanding thermally expandable particles.

[0102] The thermally expandable particles may comprise a shell comprising a thermoplastic resin and a foaming agent encapsulated inside the shell. The thermoplastic resin may comprise at least one copolymer selected from the group consisting of a vinylidene chloride-based copolymer, an acrylonitrile-based copolymer, a methacrylonitrile-based copolymer, and an acryl-based copolymer.

[0103] In an embodiment, the foaming agent encapsulated in the inside may comprise a hydrocarbon compound having 1 to 7 carbon atoms. For example, the foaming agent encapsulated in the inside may comprise a low molecular weight hydrocarbon such as ethane, ethylene, propane, propene, n-butane, isobutane, butene, isobutene, n-pentane, isopentane, neopentane, n-hexane, heptane, petroleum ether, and the like; a chlorofluorohydrocarbon such as trichlorofluoromethane (CCl.sub.3F), dichlorodifluoromethane (CCl.sub.2F.sub.2), chlorotrifluoromethane (CClF.sub.3), tetrafluoroethylene (CClF.sub.2CClF.sub.2), and the like; or tetramethylsilane, trimethylethylsilane, trimethylisopropylsilane, trimethyl-n-propylsilane, and the like. They may be used alone or in combination of two or more.

[0104] In some embodiments, the solid phase foaming agent may have a density of 25 kg/m.sup.3 or less. As a result, agglomeration and coalescence of pores can be prevented during the mixing and curing process of the raw material mixture, and pores having a uniform size and distribution can be formed inside the polishing layer. For example, the density of the solid phase foaming agent may be greater than 0 kg/m.sup.3 to 25 kg/m.sup.3 or less, 5 kg/m.sup.3 to 25 kg/m.sup.3, or 10 kg/m.sup.3 to 25 kg/m.sup.3 or less.

[0105] In some embodiments, the solid phase foaming agent may have a thermal decomposition initiation temperature (Tstart) of 95 C. to 110 C. The thermal decomposition initiation temperature may refer to the temperature at which the weight of the solid phase foaming agent begins to decrease when it is heated at a heating rate of 10 C./minute from 0 C. in a nitrogen gas atmosphere. For example, the thermal decomposition initiation temperature of the solid phase foaming agent may be 98 C. to 110 C., 100 C. to 110 C., or 100 C. to 108 C.

[0106] In some embodiments, the solid phase foaming agent may have a maximum thermal decomposition temperature (Tmax) of 130 C. to 170 C. The maximum thermal decomposition temperature of the solid phase foaming agent may refer to the temperature at which the solid phase foaming agent is completely melted when it is heated at a heating rate of 10 C./minute from 0 C. in a nitrogen gas atmosphere. For example, the maximum thermal decomposition temperature of the solid phase foaming agent may be 135 C. to 170 C., 140 C. to 165 C., or 143 C. to 160 C.

[0107] When the thermal decomposition initiation temperature and maximum thermal decomposition temperature of the solid phase foaming agent are each within the above ranges, the pore characteristics such as size, distribution, and content of pores to be formed within the polishing pad can be more precisely controlled. Accordingly, it is possible to readily prepare a polishing pad that provides a desired range of polishing amounts and dishing values.

[0108] The content of the solid phase foaming agent may be 0.5 part by weight to 5.0 parts by weight based on 100 parts by weight of the raw material mixture. For example, the content of the solid phase foaming agent may be 0.5 part by weight to 3.5 parts by weight, 0.5 part by weight to 3.0 parts by weight, 0.5 part by weight to 2.0 parts by weight, 0.5 part by weight to 1.5 parts by weight, or 0.8 part by weight to 1.4 parts by weight, based on 100 parts by weight of the composition. Within the above range, the size, distribution, and content of pores within the polishing layer can be controlled within a desired range while the hardness, tensile strength, and elongation of the polishing pad are not deteriorated.

[0109] The curing agent may comprise an amine compound and/or an alcohol compound. For example, the curing agent may comprise at least one compound selected from the group consisting of an aromatic amine, an aliphatic amine, an aromatic alcohol, and an aliphatic alcohol.

[0110] For example, the curing agent may comprise at least one selected from the group consisting of 4,4-methylenebis(2-chloroaniline) (MOCA), diethyltoluenediamine, diaminodiphenylmethane, diaminodiphenyl sulphone, m-xylylene diamine, isophoronediamine, ethylenediamine, diethylenetriamine, triethylenetetramine, polypropylenediamine, polypropylenetriamine, ethylene glycol, diethylene glycol, dipropylene glycol, butanediol, hexanediol, glycerin, trimethylolpropane, and bis(4-amino-3-chlorophenyl) methane.

[0111] The content of the curing agent may be 3.0 parts by weight to 40 parts by weight based on 100 parts by weight of the raw material mixture. For example, the content of the curing agent may be 5.0 parts by weight to 35 parts by weight or 7.0 parts by weight to 30 parts by weight based on 100 parts by weight of the raw material mixture. Within the above range, the physical properties of the polishing pad can be further improved. For example, a polishing pad having hardness, elongation, or modulus required in a CMP process can be provided.

[0112] The urethane-based prepolymer and the curing agent may be mixed at a molar equivalent ratio of 1:0.8 to 1:1.2, or a molar equivalent ratio of 1:0.9 to 1:1.1, based on the number of moles of the reactive groups in each molecule. Here, the number of moles of the reactive groups in each molecule refers to, for example, the number of moles of the isocyanate group in the urethane-based prepolymer and the number of moles of the reactive groups (e.g., amine group, alcohol group, and the like) in the curing agent. The urethane-based prepolymer and the curing agent may be added during the mixing process so as to satisfy the molar equivalent ratio described above and react with each other. As the curing reaction is carried out at the above reaction ratio, the curing reaction can be optimized, whereby it is possible to provide a polishing pad with the physical properties required for a CMP process.

[0113] In some embodiments, the raw material mixture may comprise 55 parts by weight to 96.5 parts by weight of the urethane-based prepolymer, 0.5 part by weight to 5.0 parts by weight of the solid phase foaming agent, and 3.0 parts by weight to 40 parts by weight of the curing agent based on 100 parts by weight of the raw material mixture. For example, the raw material mixture may comprise 66.5 parts by weight to 96.5 parts by weight of the urethane-based prepolymer, 0.5 part by weight to 3.5 parts by weight of the solid phase foaming agent, and 5.0 parts by weight to 35 parts by weight of the curing agent based on 100 parts by weight of the raw material mixture.

[0114] In some embodiments, the raw material mixture may further comprise a surfactant. The surfactant may prevent the pores to be formed from overlapping and coalescing with each other. For example, the surfactant may be a silicone-based nonionic surfactant. But other surfactants may be variously selected depending on the physical properties required for the polishing pad.

[0115] As the silicone-based nonionic surfactant, a silicone-based nonionic surfactant having a hydroxyl group may be used alone, or a silicone-based nonionic surfactant having a hydroxyl group and a silicone-based nonionic surfactant having no hydroxyl group may be used together.

[0116] The silicone-based nonionic surfactant having a hydroxyl group is not particularly limited as long as it is widely used in the polyurethane technology industry since it is excellent in compatibility with an isocyanate-containing compound and an active hydrogen compound. In an embodiment, examples of the silicone-based nonionic surfactant having a hydroxyl group, which is commercially available, include DOW CORNING 193 (a silicone glycol copolymer in a liquid phase having a specific gravity at 25 C. of 1.07, a viscosity at 20 C. of 465 mm.sup.2/s, and a flashpoint of 92 C.) (hereinafter referred to as DC-193) manufactured by Dow Corning.

[0117] Examples of the silicone-based nonionic surfactant having no hydroxyl group, which is commercially available, include DOW CORNING 190 (a silicone glycol copolymer having a Gardner color number of 2, a specific gravity at 25 C. of 1.037, a viscosity at 25 C. of 2,000 mm.sup.2/s, a flash point of 63 C. or higher, and an inverse solubility point (1.0% water solution) of 36 C. (hereinafter referred to as DC-190) manufactured by Dow Corning.

[0118] The content of the surfactant may be 0.1 part by weight to 2 parts by weight, 0.2 part by weight to 1.8 parts by weight, 0.2 part by weight to 1.7 parts by weight, 0.2 part by weight to 1.6 parts by weight, or 0.2 part by weight to 1.5 parts by weight, based on 100 parts by weight of the raw material mixture. Within the above range, pores derived from the foaming agent can be stably formed and maintained during the curing or molding process.

[0119] The raw material mixture may be reacted to form a solid polyurethane. For example, the isocyanate terminal group (NCO group) in the urethane-based prepolymer can react with an amine group, an alcohol group, and the like in the curing agent during the reaction. The solid phase foaming agent can be uniformly dispersed in the solid polyurethane to form a plurality of pores without participating in the curing reaction.

[0120] In an embodiment, the solid polyurethane may be prepared in a sheet form.

[0121] In some embodiments, the forming or curing process may be carried out using a mold. For example, the raw material mixture may be injected into a mold and molded. Specifically, the raw material mixture stirred in a mixing head or the like may be injected into a mold to fill the inside thereof.

[0122] In an embodiment, in the process of mixing and dispersing the urethane-based prepolymer, the solid phase foaming agent, and the curing agent, they are mixed at a rotational speed of the mixing head of 500 rpm to 10,000 rpm, specifically, 1,000 rpm to 9,000 rpm, 2,000 rpm to 9,000 rpm, 3,000 to 8,000 rpm, 4,000 to 8,000 rpm, or 5,000 rpm to 7,000 rpm. Within the above range, the shape of the pores contained in the polishing pad can be more readily controlled within a desired range.

[0123] The reaction between the urethane-based prepolymer and the curing agent is completed in the mold to thereby produce a molded body in the form that conforms to the shape of the mold.

[0124] The molded body may be appropriately sliced or cut into a sheet for the production of a polishing pad. For example, the raw material mixture may be molded in a mold having a height of 5 times to 50 times the thickness of a polishing pad to be finally produced, and the molded body is then sliced in the same thickness to produce a plurality of sheets for the polishing pads at the same time. In an embodiment, a reaction retarder as a reaction rate controlling agent may be further mixed in order to secure a sufficient solidification time.

[0125] The reaction rate controlling agent may comprise at least one selected from the group consisting of triethylenediamine, dimethylethanolamine, tetramethylbutanediamine, 2-methyl-triethylenediamine, dimethylcyclohexylamine, triethylamine, triisopropanolamine, 1,4-diazabicyclo(2,2,2) octane, bis(2-methylaminoethyl) ether, trimethylaminoethylethanolamine, N,N,N,N,N-pentamethyldiethyldimethylaminoethylamine, dimethylaminopropylamine, benzyldimethylamine, N-ethylmorpholine, N,N-dimethylaminoethylmorpholine, N,N-dimethylcyclohexylamine, 2-methyl-2-azanobornene, dibutyltin dilaurate, stannous octoate, dibutyltin diacetate, dioctyltin diacetate, dibutyltin maleate, dibutyltin di-2-ethylhexanoate, and dibutyltin dimercaptide.

Process for Preparing a Semiconductor Device

[0126] In the process for preparing a semiconductor device according to embodiments of the present invention, a semiconductor substrate may be polished using the polishing pad described above.

[0127] FIG. 5 is a schematic process flow diagram for explaining a process for preparing a semiconductor device.

[0128] Referring to FIG. 5, the polishing pad comprising a polishing layer may be mounted on a platen (e.g., step S11). A semiconductor substrate may be positioned on the polishing pad such that the polishing surface of the polishing pad and the surface (surface to be polished) of the semiconductor substrate are in contact (e.g., step S12). The surface may be in direct contact with the polishing surface of the polishing layer.

[0129] In an embodiment, a polishing slurry may be sprayed onto the polishing pad for polishing. In an embodiment, the flow rate of the polishing slurry may be controlled within the range of 10 ml/minute to 1,000 ml/minute or 50 ml/minute to 500 ml/minute.

[0130] The polishing pad and the semiconductor substrate may be rotated relative to each other to polish the surface of the semiconductor substrate (e.g., step S13). In an embodiment, the rotation direction of the polishing pad and the rotation direction of the semiconductor substrate may be the same. In an embodiment, the rotation direction of the polishing pad and the rotation direction of the semiconductor substrate may be opposite to each other.

[0131] In an embodiment, the rotation speed of the polishing pad and the rotation speed of the semiconductor substrate may be 10 rpm to 500 rpm, 30 rpm to 200 rpm, or 50 rpm to 150 rpm, respectively.

[0132] In an embodiment, the semiconductor substrate mounted on the polishing head is pressed against the polishing surface of the polishing pad at a predetermined load. The load applied to the polishing surface of the polishing pad and the surface of the semiconductor substrate by the polishing head may be 1 gf/cm.sup.2 to 1,000 gf/cm.sup.2 or 10 gf/cm.sup.2 to 800 gf/cm.sup.2.

[0133] In an embodiment, in order to maintain the polishing surface of the polishing pad in a state suitable for polishing, the process for preparing a semiconductor device may further comprise processing the polishing surface of the polishing pad with a conditioner simultaneously with polishing the wafer. The conditioning process for the polishing surface may be carried out simultaneously with the polishing of the semiconductor substrate.

[0134] The semiconductor substrate may comprise a first region having a first coefficient of thermal expansion and a second region having a second coefficient of thermal expansion on the surface thereof. As the surface of the semiconductor substrate is polished using the polishing pad, the polishing selectivity of the first region and the second region on the surface of the semiconductor substrate calculated by the dishing value after the polishing process can be adjusted within a desired range.

[0135] In an embodiment, the first region may comprise a dielectric material. For example, the first region may function as a dielectric layer or an insulation layer of a semiconductor substrate. The first region may comprise SiO.sub.2 or SiNx.

[0136] In an embodiment, the second region may comprise a metal. For example, the second region may function as a circuit wiring or a contact of a semiconductor substrate. The second region may comprise copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), or the like.

[0137] FIG. 6 is a schematic process flow diagram for explaining a process for preparing a semiconductor device.

[0138] Referring to FIG. 6, the surfaces of a first semiconductor substrate and a second semiconductor substrate may each be polished using the polishing pad according to the above embodiments (e.g., step S21).

[0139] The polishing process for the first semiconductor substrate and the second semiconductor substrate may be the same as the process described in FIG. 5. For example, the first semiconductor substrate is mounted on a head such that the upper side of the first semiconductor substrate is brought into contact with the polishing surface of the polishing pad, and the first semiconductor substrate and the polishing pad are relatively rotated to polish the upper side of the first semiconductor substrate. For example, the second semiconductor substrate is mounted on a head such that the lower side of the second semiconductor substrate is brought into contact with the polishing surface of the polishing pad, and the second semiconductor substrate and the polishing pad are relatively rotated to polish the lower side of the second semiconductor substrate.

[0140] In some embodiments, each of the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate may comprise a first region having a first coefficient of thermal expansion and a second region having a second coefficient of thermal expansion.

[0141] During the polishing process, a recess having a concave or convex shape may be formed in the second region. For example, the outermost side of the first region and the outermost side of the second region may be located at different levels or heights. As the polishing process is carried out using the polishing pad, the dishing value on each of the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate after the polishing process can be adjusted within a desired range.

[0142] The first semiconductor substrate and the second semiconductor substrate may be attached so as to face each other (e.g., step S22). For example, the first semiconductor substrate may be attached to the second semiconductor substrate such that the upper side of the first semiconductor substrate and the lower side of the second semiconductor substrate face each other.

[0143] In some embodiments, in a state where the first semiconductor substrate and the second semiconductor substrate are attached to each other, the first region of the first semiconductor substrate and the first region of the second semiconductor substrate may be in contact with each other. For example, the first region of the first semiconductor substrate may be vertically adjacent to the first region of the second semiconductor substrate, and the second region of the first semiconductor substrate may be vertically adjacent to the second region of the second semiconductor substrate.

[0144] In an embodiment, in the procedure of attaching the first semiconductor substrate and the second semiconductor substrate, a predetermined pressure may be applied to the attachment surface. As a result, a chemical bond may be formed between the first regions. For example, a hydrogen bond may be formed between the first regions in contact with each other, so that the first region of the first semiconductor substrate and the first region of the second semiconductor substrate can be chemically connected.

[0145] At least a portion of the second region of the first semiconductor substrate may be physically separated from the second region of the second semiconductor substrate. For example, since the second regions of the first semiconductor substrate and the second semiconductor substrate each have a recess shape, a gap can be formed by the second regions at the interface between the semiconductor substrates.

[0146] The first semiconductor substrate and the second semiconductor substrate may be bonded by thermal treatment. (e.g., step S23). During the procedure of thermal treatment, the second region of the first semiconductor substrate and the second region of the second semiconductor substrate may expand with each other to fill the gap between the semiconductor substrates. For example, since the second regions have a high coefficient of thermal expansion, they can have a relatively high volume expansion rate relative to the first regions. Accordingly, the second region of the first semiconductor substrate and the second region of the second semiconductor substrate can be in contact with each other without a defect in the bonding between the first regions. In addition, the thermal treatment can cause mutual diffusion between the second regions, thereby making them bonded or integrated with each other.

[0147] As semiconductor substrates are polished using the polishing pad according to embodiments of the present invention, a dishing value within a desired range can be obtained on the surface of each semiconductor substrate. As a result, defects in the bonding between semiconductor substrates can be prevented, and the second regions can be vertically in close contact with each other, thereby, for example, improving the connectivity between the circuit wirings.

[0148] In some embodiments, the thermal treatment may be carried out at a temperature of 100 C. to 400 C. In an embodiment, the thermal treatment may be carried out in stages. For example, the thermal treatment may comprise a first thermal treatment step carried out at a temperature of 200 C. or lower and a second thermal treatment step carried out at a temperature of 300 C. or higher. For example, the first thermal treatment may be carried out at a temperature of 100 C. to 200 C., and the second thermal treatment may then be carried out at a temperature of 300 C. to 400 C. Within the above ranges, the contact between the second regions can be further enhanced while damage and lifting due to high temperatures are prevented. As a result, the bonding stability between semiconductor substrates can be further enhanced, and high-quality semiconductor devices can be prepared.

[0149] For example, in the procedure of first thermal treatment, the bonding strength between the first regions can be further increased. In the temperature range of first thermal treatment, a covalent bond may be formed between the first regions, and stronger contact than the case where a hydrogen bond is formed can be achieved. In the temperature range of second thermal treatment, the mutual diffusion phenomenon between the second regions can be further facilitated, and the second regions can be more stably connected.

[0150] In addition, as the dishing value of a semiconductor substrate is controlled within the above range by the polishing pad, the amount of thermal expansion of the first region and the amount of thermal expansion of the second region can be controlled to be substantially similar during the procedure of thermal treatment. The amount of thermal expansion in each region may be calculated by the coefficient of thermal expansion in each region (mm/mm C.)the thickness of each region after polishing (nm)the temperature change due to thermal treatment ( C.).

[0151] In some embodiments, the difference between the amount of thermal expansion of the first region and the amount of thermal expansion of the second region may be 1.0 nm or less, 0.8 nm or less, 0.6 nm or less, 0.5 nm or less, 0.3 nm or less, 0.2 nm or less, 0.1 nm or less, 0.01 nm or less, 0.005 nm or less, or 0.001 nm or less, as an absolute value.

[0152] As the difference between the amount of thermal expansion of the first region and the amount of thermal expansion of the second region decreases, the thickness difference of each region decreases, and the upper side of the first region and the upper side of the second region can be positioned at substantially the same level after thermal treatment. For example, if the value obtained by subtracting the amount of thermal expansion of the first region from the amount of thermal expansion of the second region exceeds 1.0 nm, a gap may be formed at the bonding surface of the first regions, as explained through FIG. 2c. For example, if the value obtained by subtracting the amount of thermal expansion of the second region from the amount of thermal expansion of the first region exceeds 1.0 nm, a gap may be formed at the bonding surface of the second regions, as explained through FIG. 3c.

[0153] As the difference between the amount of thermal expansion of the first region and the amount of thermal expansion of the second region is controlled within the above range, even if the semiconductor substrates are thermally treated in a bonded state, the first region and the second region can be positioned at substantially the same height or level, so that no gap may be formed at the bonding surface.

[0154] Hereinafter, the present invention is explained in detail by the following Examples. However, these examples are set forth to illustrate the present invention, and the scope of the present invention is not limited thereto.

EMBODIMENTS FOR CARRYING OUT THE INVENTION

Example

Preparation of a Urethane-Based Prepolymer

[0155] Toluene diisocyanate (TDI, BASF) as an isocyanate compound and polytetramethylene ether glycol (PTMEG, Korea PTG) as a polyol were mixed such that the content of the NCO group was 9.1% by weight and then reacted. In order to minimize side reactions during the synthesis, the inside of the reactor was filled with nitrogen (N.sub.2) as an inert gas at a reaction temperature of 75 C. with stirring for 3 hours to carry out the reaction, thereby preparing a urethane-based prepolymer having a content of the NCO group of 9.1% by weight.

Example 1

[0156] The urethane-based prepolymer prepared above, triethylenediamine (Dow) as a curing agent, and microcapsules (Expancel 044DU20, Noutyon) as a solid phase foaming agent were used.

[0157] The solid phase foaming agent was measured to have an average particle size (D.sub.50) of 6 m to 9 m, a thermal decomposition initiation temperature (Tstart) of 100 C. to 108 C., a maximum thermal decomposition temperature (Tmax) of 143 C. to 160 C., and a density of 25 kg/m.sup.3 or less. In addition, the elemental content of the solid phase foaming agent was measured using an inductively coupled plasma emission spectrometer (Aglient 5110 ICP-OES). The composition ratio of elements contained in the solid phase foaming agent was measured as Ca:Fe:Mg:Na:Si:Zn=38:128:76:242:39,267:32 on a weight basis.

[0158] In a casting machine equipped with feeding lines for a urethane-based prepolymer, a curing agent, an inert gas, and a solid phase foaming agent, the urethane-based prepolymer prepared above was charged, the curing agent of triethylenediamine was charged to the curing agent tank, and the purified solid phase foaming agent was quantified in an amount of 2.0 parts by weight based on 100 parts by weight of the raw material mixture and charged to the prepolymer tank at the same time.

[0159] The urethane-based prepolymer, the curing agent, and the solid phase foaming agent were fed to the mixing head and stirred at a rotation speed of 6,000 rpm. The molar equivalent ratio of the NCO group in the urethane-based prepolymer to the reactive groups in the curing agent was adjusted to 1:1, and the total feed rate was maintained at a rate of 10 kg/minute.

[0160] The mixed raw materials (i.e., raw material mixture) were injected into a mold (1,000 mm1,000 mm3 mm) and reacted to obtain a molded article in the form of a solid cake. The top and bottom of the molded body were each ground by a thickness of 0.5 mm to obtain an upper pad having a thickness of 2 mm.

[0161] The upper pad was subjected to the steps of surface milling and groove forming and laminated with a lower pad by a hot melt adhesive, thereby preparing a polishing pad.

Example 2

[0162] A polishing pad was prepared in the same manner as in Example 1, except that the composition ratio of elements of the solid phase foaming agent in Example 1 was changed to Ca:Fe:Mg:Na:Si:Zn=21:64:27:189:27,500:5 on a weight basis.

Example 3

[0163] A polishing pad was prepared in the same manner as in Example 1, except that the composition ratio of elements of the solid phase foaming agent in Example 1 was changed to Ca:Fe:Mg:Na:Si:Zn=111:2:50:383:43,917:15 on a weight basis.

Comparative Example 1

[0164] A polishing pad was prepared in the same manner as in Example 1, except that the composition ratio of elements of the solid phase foaming agent in Example 1 was changed to Ca:Fe:Mg:Na:Si:Zn=45:65:38:184:27,020:19 on a weight basis.

Comparative Example 2

[0165] A polishing pad was prepared in the same manner as in Example 1, except that the composition ratio of elements of the solid phase foaming agent in Example 1 was changed to Ca:Fe:Mg:Na:Si:Zn=35:3:63:354:38,558:3 on a weight basis.

Test Example 1: Measurement of the Diameter Distribution of a Plurality of Pores

[0166] The polishing pads prepared in the Examples and Comparative Examples were each cut into a square of 1 cm1 cm (thickness: 2 mm), and then a 3D CT-scan (GE) was performed. The diameters of the plurality of pores within the polishing pad were measured using the 3D CT-scan, from which the volume of each pore was calculated.

[0167] The pore volume distribution was obtained by listing the pores in order of increasing pore diameter. In the volume distribution of pores, Dn.sub.50 was measured as the pore diameter at a volume fraction of 50%, Dn.sub.10 was measured as the pore diameter at a volume fraction of 10%, and Dn.sub.90 was measured as the pore diameter at a volume fraction of 90%.

[0168] FIG. 7 is a cross-sectional image obtained by a 3D CT-scan of the polishing pad of Example 1. Referring to FIG. 7, it was confirmed in Example 1 that the plurality of pores had a uniform diameter and that the pores were uniformly distributed within the polishing pad.

Test Example 2: Measurement of the Polishing Amount and Dishing Value

[0169] Cu was deposited on the upper side of a patterned SiO.sub.2 wafer, and the upper side of the wafer was polished to prepare a semiconductor substrate patterned with a Cu pad on a SiO.sub.2 film. The SiO.sub.2 film had a coefficient of thermal expansion of 5.710.sup.7 mm/mm C., and the Cu pad had a coefficient of thermal expansion of 2.010.sup.5 mm/mm C. Here, polishing was performed until the upper side of the SiO.sub.2 film and the upper side of the Cu pad were positioned at the same level on the polished surface of the semiconductor substrate such that the SiO.sub.2 film was exposed.

[0170] Thereafter, the polished surface of the semiconductor substrate was further polished for 10 seconds to perform an additional polishing process, and the dishing value due to the additional polishing process was measured.

[0171] The polishing process and the additional polishing process were carried out using a CMP system (POLI-400 LM, G&P Technology) under the conditions of 20 C., a rotation speed of the polishing pad of 93 rpm, a rotation speed of the object to be polished of 87 rpm, and a polishing load of 5.0 psi, while a ceria slurry (ACS-580, KC Tech) was sprayed.

[0172] The dishing value was measured by calculating the difference in thickness change between the SiO.sub.2 film and the Cu pad before and after the additional polishing process. Since the SiO.sub.2 film and the Cu pad had the same thickness before the additional polishing process, the difference in thickness change was calculated by measuring the lowest thickness of the SiO.sub.2 film and the Cu pad after the additional polishing process, respectively, and subtracting the lowest thickness of the Cu pad from the lowest thickness of the SiO.sub.2 film. The thickness measurements were carried out using an atomic force microscope (AFM), and the minimum thickness after the additional polishing process was measured as the thickness of the most polished portion.

TABLE-US-00001 TABLE 1 Polishing Pore diameter distribution characteristics Dn.sub.10 Dn.sub.50 Dn.sub.90 Dishing value (m) (m) (m) (nm) Ex. 1 16.9 22.4 27.4 2.23 Ex. 2 18.2 27.3 38 2.91 Ex. 3 15.8 21.1 26.2 1.52 C. Ex. 1 20.9 33.3 47.9 5.07 C. Ex. 2 14.9 20.4 25.4 3.82

Preparation of a Semiconductor Device

[0173] The semiconductor substrate prepared above was prepared as an upper substrate and a lower substrate. The upper and lower substrates were attached with their polished surfaces in contact with each other and pressurized at 15 N. In such an event, the upper and lower substrates were aligned and attached with the Cu pads facing each other and the SiO.sub.2 films facing each other. While the upper and lower substrates were attached, they were thermally treated at 150 C. for 1 hour by heating from 20 C. to 150 C. and then thermally treated at 350 C. for 1 hour by heating to 350 C. to prepare a semiconductor device.

Test Example 3: Evaluation of Bonding

[0174] In the Examples and Comparative examples, the bonding between the upper substrate and the lower substrate was evaluated. Specifically, the amount of thermal expansion of the SiO.sub.2 film (the amount of first thermal expansion) and the amount of thermal expansion of the Cu pad (the amount of second thermal expansion) were calculated, respectively. The bonding properties were evaluated by calculating the difference in thermal expansion by subtracting the amount of first thermal expansion from the amount of second thermal expansion. As the difference between the amount of first thermal expansion and the amount of second thermal expansion is smaller, the upper side of the SiO.sub.2 film and the upper side of the Cu pad can be positioned at substantially the same level upon the thermal treatment; thus, the bonding between the upper substrate and the lower substrate can be improved.

[0175] The amount of first thermal expansion was calculated as the coefficient of thermal expansion of SiO.sub.2the thickness of the SiO.sub.2 film after the additional polishing processthe temperature difference before and after the thermal treatment. The amount of second thermal expansion was calculated as the coefficient of thermal expansion of Cuthe thickness of the Cu pad after the additional polishing processthe temperature difference before and after the thermal treatment.

[0176] The temperature difference before and after the thermal treatment was 330 C., which was the difference between the final thermal treatment temperature and the initial temperature before thermal treatment. The coefficient of thermal expansion of SiO.sub.2 was 5.710.sup.7 mm/mm C., the coefficient of thermal expansion of Cu was 2.010.sup.5 mm/mm C., and the thickness of the SiO.sub.2 film after the additional polishing process was set to 2.2954 nm. The thickness of the Cu pad after the additional polishing process was calculated by subtracting the dishing value from the thickness of the SiO.sub.2 film. In Table 2, the unit of the difference of thermal expansion is (10.sup.2 nm).

TABLE-US-00002 TABLE 2 Difference in thermal expansion Ex. 1 0 Ex. 2 0.449 Ex. 3 0.469 C. Ex. 1 1.87 C. Ex. 2 1.05

[0177] Referring to Table 2, in the Examples, the dishing value by the polishing pad was 3.5 nm or less, and the difference in thermal expansion between the Cu pad and the SiO.sub.2 film in the bonding process of semiconductor substrates was controlled to an absolute value of 1.010.sup.2 nm or less. Accordingly, in the semiconductor devices prepared in the Examples, the bonding quality of the semiconductor substrates and the connectivity between the Cu pads were enhanced as compared with the Comparative Examples.

[0178] In Example 1, the amount of thermal expansion of the Cu pad and the amount of thermal expansion of the SiO.sub.2 film were substantially the same. In Example 2, the dishing value was increased from Example 1, and the difference in thermal expansion showed a negative value, indicating that the amount of thermal expansion of the Cu pad was smaller than that of the SiO.sub.2 film. In Example 3, the dishing value was reduced from Example 1, so that the difference in thermal expansion showed a positive value.

REFERENCE NUMERAL OF THE DRAWINGS

[0179] 100: semiconductor substrate, 105: base substrate, 110: first region, 120: second region, 125: recess, 130: gap, 10, 200: polishing pad, 12, 250: polishing layer, 14: adhesive layer, 16: support layer.