Nanochannel gallium nitride-based device and manufacturing method thereof

Abstract

A nanochannel GaN-based device includes: a substrate layer, a nucleation layer, a buffer layer, a channel region, an insertion layer, a barrier layer, a cap layer, a first highly n.sup.+-doped material layer, a second n.sup.+-doped material layer, a source electrode, a drain electrode, and a gate electrode. A first arrayed pattern edge is formed on a side of the first n.sup.+-doped material layer facing towards the drain electrode. A second arrayed pattern edge is formed on a side of the second n.sup.+-doped material layer facing towards the source electrode. A part of the channel region, the insertion layer, the barrier layer and the cap layer form an arrayed nanochannel structure between a source electrode and a drain electrode. The first arrayed pattern edge is interdigitated with an end of the arrayed nanochannel structure. The second arrayed pattern edge is interdigitated with another end of the arrayed nanochannel structure.

Claims

1. A nanochannel gallium nitride (GaN)-based device, comprising: a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel region (4), an insertion layer (5), a barrier layer (6), a cap layer (7), a first n.sup.+-doped material layer (8), a second n.sup.+-doped material layer (9), a source electrode (10), a drain electrode (11), and a gate electrode (12); wherein the substrate layer (1), the nucleation layer (2), the buffer layer (3), the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) are sequentially stacked in that order; wherein the first n.sup.+-doped material layer (8) is disposed in a source electrode region, and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the first n.sup.+-doped material layer (8) is disposed under channels of the channel region (4), the first n.sup.+-doped material layer (8) comprises a first arrayed pattern edge (81) facing towards the drain electrode (11), and the source electrode (10) is disposed on the first n.sup.+-doped material layer (8); wherein the second n.sup.+-doped material layer (9) is disposed in a drain electrode region and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the second n.sup.+-doped material layer (9) is disposed under the channels of the channel region (4), the second n.sup.+-doped material layer (9) comprises a second arrayed pattern edge (91) facing towards the source electrode (10), and the drain electrode (11) is disposed on the second n.sup.+-doped material layer (9); wherein a part of the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) together form an arrayed nanochannel structure (71) between the source electrode region and the drain electrode region, the first arrayed pattern edge (81) is interdigitated with an end of the arrayed nanochannel structure (71), and the second arrayed pattern edge (91) is interdigitated with another end of the arrayed nanochannel structure (71); and wherein the gate electrode (12) is disposed between the first n.sup.+-doped material layer (8) and the second n.sup.+-doped material layer (9), on the arrayed nanochannel structure (71) and in recesses (72) defined by the arrayed nanochannel structure (71), to form a three-dimensional gate-all-around structure.

2. The nanochannel GaN-based device as claimed in claim 1, wherein a material of the substrate layer (1) comprises one or more selected from the group consisting of sapphire, silicon carbide and silicon; and wherein a material of the barrier layer (6) comprises one or more selected from the group consisting of aluminum nitride (AlN), indium aluminum nitride (InAlN), scandium aluminum nitride (ScAlN), and aluminum gallium nitride (AlGaN).

3. The nanochannel GaN-based device as claimed in claim 1, wherein a material of each of the first n.sup.+-doped material layer (8) and the second n.sup.+-doped material layer (9) comprises at least one of n.sup.+-GaN and n.sup.+-InGaN.

4. The nanochannel GaN-based device as claimed in claim 1, wherein the first arrayed pattern edge (81) comprises a plurality of first rectangular structures (811), and the plurality of first rectangular structures (811) are disposed evenly along an edge of the first n.sup.+-doped material layer (8); and wherein the second arrayed pattern edge (91) comprises a plurality of second rectangular structures (911), and the plurality of second rectangular structures (911) are disposed evenly along an edge of the second n.sup.+-doped material layer (9).

5. The nanochannel GaN-based device as claimed in claim 4, wherein a length of each of the plurality of first rectangular structures (811) is in a range of 20-1500 nanometers (nm), a width of each of the plurality of first rectangular structures (811) is in a range of 20-2000 nm, and a spacing between adjacent two of the plurality of first rectangular structures (811) is in a range of 20-2000 nm; and wherein a length of each of the plurality of second rectangular structures (911) is in a range of 20-1500 nm, a width of each of the plurality of second rectangular structures (911) is in a range of 20-2000 nm, and a spacing between adjacent two of the plurality of second rectangular structures (911) is in a range of 20-2000 nm.

6. The nanochannel GaN-based device as claimed in claim 1, wherein the arrayed nanochannel structure (71) comprises at least one nanochannel (73), and the at least one nanochannel (73) is disposed evenly along a gate width direction of the gate electrode (12).

7. The nanochannel GaN-based device as claimed in claim 6, wherein a width of each of the at least one nanochannel (73) is in a range of 20-2000 nm, and a spacing between adjacent two of the at least one nanochannel (73) is in a range of 20-2000 nm.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 illustrates a top view of an overall structure of a nanochannel GaN-based device according to an embodiment of the disclosure.

(2) FIG. 2 illustrates a cross-sectional view of an A-A plane illustrated in FIG. 1.

(3) FIG. 3 illustrates a cross-sectional view of a B-B plane illustrated in FIG. 1.

(4) FIG. 4 illustrates a cross-sectional view of a C-C plane illustrated in FIG. 1.

(5) FIG. 5 illustrates a cross-sectional view of a D-D plane illustrated in FIG. 1.

(6) FIGS. 6A-6L illustrate schematic process diagrams of a manufacturing method of the nanochannel GaN-based device according to an embodiment of the disclosure.

(7) FIG. 7 illustrates a top view corresponding to FIG. 6C.

DETAILED DESCRIPTION OF EMBODIMENTS

(8) The disclosure will be further described in detail with specific embodiments below, but embodiments of the disclosure are not limited to these.

Embodiment 1

(9) Referring to FIGS. 1-5, FIG. 1 illustrates a top view of an overall structure of a nanochannel GaN-based device according to an embodiment of the disclosure, FIG. 2 illustrates a cross-sectional view of an A-A plane illustrated in FIG. 1, FIG. 3 illustrates a cross-sectional view of a B-B plane illustrated in FIG. 1, FIG. 4 illustrates a cross-sectional view of a C-C plane illustrated in FIG. 1, and FIG. 5 illustrates a cross-sectional view of a D-D plane illustrated in FIG. 1.

(10) The nanochannel GaN-based device in the embodiment includes: a substrate layer 1, a nucleation layer 2, a buffer layer 3, a channel region 4, an insertion layer 5, a barrier layer 6, a cap layer 7, a first n.sup.+-doped material layer 8, a second n.sup.+-doped material layer 9, a source electrode 10, a drain electrode 11 and a gate electrode 12.

(11) The substrate layer 1, the nucleation layer 2, the buffer layer 3, the channel region 4, the insertion layer 5, the barrier layer 6 and the cap layer 7 are sequentially stacked in that order.

(12) The first n.sup.+-doped material layer 8 is disposed in a source electrode region, and penetrates through the cap layer 7, the barrier layer 6, and the insertion layer 5, a bottom of the first n.sup.+-doped material layer 8 is disposed under channels of the channel region 4, a first arrayed pattern edge 81 is formed on a side of the first n.sup.+-doped material layer 8 facing towards the drain electrode 11, and the source electrode 10 is disposed on the first n.sup.+-doped material layer 8. The source electrode 10 forms an ohmic metal electrode on the first n.sup.+-doped material layer 8.

(13) Specifically, a first recess 80 is formed in the source electrode region by etching a part of the cap layer 7, a part of the barrier layer 6, a part of the insertion layer 5 and a part of the channel region 4 in the source electrode region. A depth of the first recess 80 extends to below the channels of the channel region 4. The first arrayed pattern edge 81 is disposed on a side of the first recess 80 facing towards the drain electrode 11, and the first n.sup.+-doped material layer 8 is filled in the first recess 80.

(14) The second n.sup.+-doped material layer 9 is disposed in a drain electrode region and penetrates through the cap layer 7, the barrier layer 6, and the insertion layer 5, a bottom of the second n.sup.+-doped material layer 9 is disposed under the channels of the channel region 4, a second arrayed pattern edge 91 is formed on a side of the second n.sup.+-doped material layer 9 facing towards the source electrode 10, and the drain electrode 11 is disposed on the second n.sup.+-doped material layer 9.

(15) Specifically, a second recess 90 is formed in the drain electrode region by etching a part of the cap layer 7, a part of the barrier layer 6, a part of the insertion layer 5 and a part of the channel region 4 in the drain electrode region. A depth of the second recess 90 extends to below the channels of the channel region 4. The second arrayed pattern edge 91 is disposed on the side of the second recess 90 facing towards the source electrode 10, and the second n.sup.+-doped material layer 9 is filled in the second recess 90. The drain electrode 11 forms an ohmic metal electrode on the second n.sup.+-doped material layer 9.

(16) The nanochannel GaN-based device of the embodiment includes: the first arrayed pattern edge 81 formed on the side of the first n.sup.+-doped material layer 8 facing towards the drain electrode 11, the second arrayed pattern edge 91 formed on the side of the second n.sup.+-doped material layer 9 facing towards the source electrode 10, the source electrode 10 disposed on the first n.sup.+-doped material layer 8, and the drain electrode 11 disposed on the second n.sup.+-doped material layer 9, to thereby form a nanochannel structure device based on patterned ohmic contact, effectively reducing the contact resistance of the device, forming better ohmic contact, further lowering the knee voltage of the device, and improving the working efficiency of the device.

(17) A part of the channel region 4, the insertion layer 5, the barrier layer 6 and the cap layer 7 together form an arrayed nanochannel structure 71 between the source electrode region and the drain electrode region. The first arrayed pattern edge 81 is interdigitated with an end of the arrayed nanochannel structure 71, and the second arrayed pattern edge 91 is interdigitated with another end of the arrayed nanochannel structure 71.

(18) Specifically, arrayed recesses are formed by etching a part of the cap layer 7, a part of the barrier layer 6, a part of the insertion layer 5 and a part of the channel region 4 between the source electrode region and the drain electrode region. A depth of each arrayed recess extends to below the channels of the channel region 4. Meanwhile, retained parts of the cap layer 7, the barrier layer 6, the insertion layer 5 and the channel region 4 between the arrayed recesses form the arrayed nanochannel structure 71. In an embodiment, the first arrayed pattern edge 81 is disposed on an end of the arrayed recesses and matches with the end of the arrayed nanochannel structure 71, and the second arrayed pattern edge 91 is disposed on another end of the arrayed recesses and matches with the another end of the arrayed nanochannel structure 71.

(19) The gate electrode 12 is disposed between the first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9, on the arrayed nanochannel structure 71 and in recesses 72 (i.e., the arrayed recesses) defined by the arrayed nanochannel structure 71, to form a three-dimensional gate-all-around structure.

(20) Specifically, the gate electrode 12 includes a top gate 121 and side gates 122, the top gate 121 is disposed on the side gates 122 and on the arrayed nanochannel structure 71, and the side gates 122 are disposed in the recesses 72 defined by the arrayed nanochannel structure 71. Two sidewalls of the side gates 122 and the top gate 121 may simultaneously modulate the two-dimensional electron gas in the channels, thereby forming a three-dimensional gate-all-around structure.

(21) The gate electrode of the nanochannel GaN-based device of the embodiment forms the three-dimensional gate-all-around structure. The two-dimensional electron gas in a channel is modulated from the side gates at two sides of the channel and from the top gate on the channel, thereby effectively suppressing the short-channel effect, enhancing the control ability of the gate electrode, improving the linearity of the device, and lowering the knee voltage of the device.

(22) In a specific embodiment, a material of the substrate layer 1 includes one or more selected from the group consisting of sapphire, SiC and Si. A material of the barrier layer 6 includes one or more selected from the group consisting of AlN, InAlN, ScAlN, and AlGaN. A material of each of the first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9 includes at least one of n.sup.+-GaN and n.sup.+-InGaN.

(23) In a specific embodiment, the first arrayed pattern edge 81 includes multiple first rectangular structures 811, and the first rectangular structures 811 are disposed evenly along an edge of the first n.sup.+-doped material layer 8.

(24) Specifically, the first rectangular structures 811 disposed evenly are formed on the edge of the first n.sup.+-doped material layer 8 facing towards the drain electrode 11. Optionally, a length L.sub.c1 of each first rectangular structure 811 is in a range of 20-1500 nm, a width W.sub.c1 of each first rectangular structure 811 is in a range of 20-2000 nm, and a spacing W.sub.d1 between adjacent two of the first rectangular structures 811 is in a range of 20-2000 nm.

(25) In a specific embodiment, the second arrayed pattern edge 91 includes multiple second rectangular structures 911, and the second rectangular structures 911 are disposed evenly along an edge of the second n.sup.+-doped material layer 9.

(26) Specifically, the second rectangular structures 911 disposed evenly are formed on the edge of the second n.sup.+-doped material layer 9 near the source electrode 10. Optionally, A length L.sub.c2 of each second rectangular structure 911 is in a range of 20-1500 nm, a width W.sub.c2 of each second rectangular structure 911 is in a range of 20-2000 nm, and a spacing W.sub.d2 between adjacent two of the second rectangular structures 911 is in a range of 20-2000 nm.

(27) In a specific embodiment, the first arrayed pattern edge 81 and the second arrayed pattern edge 91 have a same structure, i.e., the first arrayed pattern edge 81 and the second arrayed pattern edge 91 have the same number of rectangular structures, and lengths, widths and spacings of the rectangular structures of the first arrayed pattern edge 81 and lengths, widths and spacings of the rectangular structures of the second arrayed pattern edge 91 are the same.

(28) It should be noted that, the structures of the first arrayed pattern edge 81 and the second arrayed pattern edge 91 are not limited to the aforementioned rectangular structures, and may be smooth arc-shaped edge structures, serrated edge structures and trapezoidal edge structures, etc., without further restrictions in the embodiment.

(29) In a specific embodiment, the arrayed nanochannel structure 71 includes at least one nanochannel 73, and when the at least one nanochannel 73 is at least three in number, the nanochannels 73 are disposed evenly along a gate width direction of the gate electrode 12.

(30) It can be understood that, a number of the nanochannels 73 of the arrayed nanochannel structure 71 is n, and n is greater than or equal to 1. When there are multiple nanochannels 73, the spacing between adjacent two nanochannels 73 is same and uniform.

(31) Specifically, a width W.sub.ch of each nanochannel 73 is in a range of 20-2000 nm, and a spacing W.sub.d between adjacent two nanochannels 73 is in a range of 20-2000 nm.

(32) In summary, the nanochannel GaN-based device of the embodiment can significantly reduce the knee voltage of the device, suppress the short-channel effect, thus improving the work efficiency and linearity, thereby realizing a higher performance millimeter wave power device.

Embodiment 2

(33) On a basis of the embodiment 1, this embodiment provides a manufacturing method of the nanochannel GaN-based device.

(34) Referring to FIGS. 6A-6L, FIGS. 6A-6L illustrate schematic process diagrams of the manufacturing method of the nanochannel GaN-based device according to the embodiment of the disclosure.

(35) This embodiment illustrates the manufacturing of a low-contact-resistance GaN-based device, which uses the sapphire as a substrate. Depths of the source and drain regrowth regions and the nanochannel recesses, i.e., the depths of the first recess 80, the second recess 90, and each of the arrayed recesses, are 45 nm. The recess patterns are shown in FIG. 7, which is a top view corresponding to FIG. 6C. The width W.sub.ch of each nanochannel 73 is 400 nm, and the length L.sub.ch of each nanochannel 73 is 1.5 micrometers (m). The first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9 use highly doped n.sup.+-GaN, which is prepared using molecular beam epitaxy (MBE) process.

(36) Specifically, the manufacturing method of the nanochannel GaN-based device includes following steps S1-S10.

(37) S1, the nucleation layer 2, the buffer layer 3, the channel region 4, the insertion layer 5, the barrier layer 6 and the cap layer 7 are sequentially grown in that order on the substrate layer 1, as shown in FIG. 6A.

(38) Specifically, on the sapphire substrate layer 1, the metal-organic chemical vapor deposition (MOCVD) process is used to sequentially grow the AlN nucleation layer 2, the GaN buffer layer 3, the GaN channel region 4, the AlN insertion layer 5, the InAlN barrier layer 6 and the GaN cap layer 7 in that order.

(39) S2, a mask layer 70 is grown on the cap layer 7, as shown in FIG. 6B.

(40) Specifically, the plasma enhanced chemical vapor deposition (PECVD) process is used to depositing the SiO.sub.2 mask layer 70 on the cap layer 7. Specifically, silane (SiH.sub.4) and nitrous oxide (N.sub.2O) are used as precursors to deposit SiO.sub.2 at an oven temperature of 300 C. as a regrown mask layer 70. A thickness of the mask layer 70 is in a range of 40-400 nm.

(41) S3, patterns of an ohmic regrowth region and nanochannels 73 are defined on the mask layer 70; and a part of the cap layer 7, a part of the barrier layer 6, a part of the insertion layer 5 and a part of the channel region 4 between the ohmic regrowth region and the nanochannels 73 are etched, to thereby form the first recess 80 disposed in a source arrayed pattern region, the second recess 90 disposed in a drain arrayed pattern region and the arrayed nanochannel structure 71 disposed between the source arrayed pattern region and the drain arrayed pattern region; where the arrayed nanochannel structure 71 retains a part of the mask layer 70; as shown in FIGS. 6C-6D. Step S3 includes following steps S31-S33.

(42) S31, photoresist is spin-coated on the mask layer 70, and exposure and development are performed to form the patterns of the ohmic regrowth region and the nanochannels 73 and expose the mask layer 70.

(43) Specifically, the photoresist is coated on the SiO.sub.2 mask layer 70, with a thickness of the photoresist about 1.2 m, followed by pre-baking for 1 minute. Then, the exposure is performed on the pattern regions of the ohmic regrowth region and the nanochannels 73, followed by post-baking for 1 minute. After the post-baking is completed and a sample temperature has dropped to room temperature, the development is performed to remove the photoresist in the patterned region, thereby completing the photolithography, thus forming the patterns of the ohmic regrowth region and the nanochannels 73 while exposing a part of the mask layer 70 in these regions, as shown in FIG. 7.

(44) S32, an exposed part of the mask layer 70 is removed by using an F-based dry etching process, and the part of the cap layer 7, the part of the barrier layer 6, the part of the insertion layer 5 and the part of the channel region 4 between the ohmic regrowth region and the nanochannels 73 are removed by using a Cl-based dry etching process, to thereby form the first recess 80, the second recess 90 and the arrayed nanochannel structure 71.

(45) Specifically, before etching, the sample obtained in step S31 is baked on a hot plate at 100 C. for 1 minute to enhance the etch resistance of the photoresist. Then, an inductively coupled plasma (ICP) etching process is used to perform the F-based dry etching process to remove the exposed part of the SiO.sub.2 mask layer 70 after photolithography. Subsequently, the Cl-based ICP etching is used to remove the part of the GaN cap layer 7, the part of the InAlN barrier layer 6, the part of the AlN insertion layer 5 and the part of the GaN channel layer 4 under the SiO.sub.2 mask layer 70. The etch is performed to below the channels of the GaN channel layer 4, with an etching depth of 45 nm, forming the first recess 80, the second recess 90, and the arrayed nanochannel structure 71, as shown in FIGS. 6C-6D. FIG. 6C corresponds to the D-D plane illustrated in FIG. 1, and FIG. 6D corresponds to the C-C plane illustrated in FIG. 1. S33, the photoresist is removed after etching.

(46) Specifically, the sample obtained in step S32 is placed into acetone and isopropanol sequentially in that order for ultrasonic cleaning to remove the photoresist on the surface, followed by rinsing with ultrapure water and then drying.

(47) S4, n.sup.+-doped material layers are grown in the first recess 80, the second recess 90 and recesses 72 defined by the arrayed nanochannel structure 71, and on the retained part of the mask layer 70, as show in FIGS. 6E-6F. FIG. 6E corresponds to the D-D plane illustrated in FIG. 1, and FIG. 6F corresponds to the C-C plane illustrated in FIG. 1.

(48) Specifically, the MBE process is used to grow the highly doped n.sup.+-GaN layers. The doping element includes Si. The doping concentration of the Si is 110.sup.20 cm.sup.3. the growth thickness is 80 nm.

(49) S5, the n.sup.+-doped material layers on the arrayed nanochannel structure 71 between the source arrayed pattern region and the drain arrayed pattern region, and in the recesses 72 defined by the arrayed nanochannel structure 71 are removed, and the n.sup.+-doped material layers in the source arrayed pattern region and the drain arrayed pattern region are retained to form the first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9, as shown in FIGS. 6G-6H. Step S5 specifically includes following steps S51-S53.

(50) S51, a rectangular region between the source arrayed pattern region and the drain arrayed pattern region is defined through photolithography on the n.sup.+-doped material layers.

(51) Specifically, the photoresist is coated on the n.sup.+-GaN material layers with a thickness of the photoresist about 0.7 m, followed by pre-baking for 1 minute; then the exposure is performed on the rectangular region between the source arrayed pattern region and the drain arrayed pattern region, followed by post-baking for 1 minute; after the baking is completed and the sample temperature has dropped to room temperature, the development is performed to remove the photoresist in the rectangular region between the source arrayed pattern region and the drain arrayed pattern region, completing the photolithography.

(52) S52, the n.sup.+-doped material layers on the arrayed nanochannel structure 71 between the source arrayed pattern region and the drain arrayed pattern region, and in the recesses 72 defined by the arrayed nanochannel structure 71 are etched, and the n.sup.+-doped material layers in the source arrayed pattern region and the drain arrayed pattern region are retained to form the first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9.

(53) Specifically, the photoresist and the SiO.sub.2 mask layer 70 are used as an etch mask for dry etching, the n.sup.+-GaN material layers on the rectangular region between the source arrayed pattern region and the drain arrayed pattern region are removed through the Cl-based ICP etching, i.e., the n.sup.+-doped material layers on the arrayed nanochannel structure 71 and in the recesses 72 defined by the arrayed nanochannel structure 71 are etched and removed, with an etching depth of 100 nm. The retained part of n.sup.+-GaN material layers form the first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9, as shown in FIGS. 6G-6H. FIG. 6G corresponds to the D-D plane illustrated in FIG. 1, and FIG. 6H corresponds to the C-C plane illustrated in FIG. 1.

(54) S53, the photoresist is removed after etching.

(55) Specifically, the sample obtained in step S52 is placed into acetone and isopropanol sequentially in that order for ultrasonic cleaning to remove the photoresist on the surface, followed by rinsing with ultrapure water and then drying.

(56) S6, the mask layer 70 on the arrayed nanochannel structure 71 and the cap layer 7 is removed, as shown in FIGS. 6I-6J. FIG. 6I corresponds to the D-D plane illustrated in FIG. 1, and FIG. 6J corresponds to the C-C plane illustrated in FIG. 1.

(57) Specifically, the sample obtained in step S5 is soaked in a hydrogen fluoride (HF) solution (HF:H.sub.2O=2:3) for 15 minutes to completely etch the SiO.sub.2 mask layer 70 on the device surface and then rinsed with ultrapure water for 2 minutes followed by drying with nitrogen gas to obtain a dried sample; subsequently, the dried sample is placed sequentially into acetone, stripping solution, acetone, and isopropanol in that order for ultrasonic cleaning, and then rinsed with ultrapure water followed by drying.

(58) S7, the source electrode 10 is prepared on the first n.sup.+-doped material layer 8, and the drain electrode 11 is prepared on the second n.sup.+-doped material layer 9, as shown in FIG. 6K. Step S7 specifically includes following steps S71-S73.

(59) S71, a source electrode pattern is formed through photolithography on the first n.sup.+-doped material layer 8, and a drain electrode pattern is formed through photolithography on the second n.sup.+-doped material layer 9.

(60) Specifically, a double-layer photoresist is coated on the sample obtained in step S6, with a thickness of lift-off resist at a bottom layer about 0.35 m and a thickness of photoresist at a top layer about 0.56 m; then, the exposure is performed on the metal electrode pattern region, followed by post-baking for 1 minute; after the post-baking is completed and a sample temperature has dropped the room temperature, the development is performed to remove the photoresist on the metal electrode pattern region, thereby completing the photolithography.

(61) S72, titanium/aurum (Ti/Au) metal electrodes are deposited via an electron-beam evaporation device.

(62) Specifically, the residual photoresist is removed from the exposed region by using a plasma resist remover, and then the electron-beam evaporation device is used to sequentially evaporate a Ti layer with a thickness of 20 nm and an Au layer with a thickness of 200 nm.

(63) S73, the metal in the unexposed region is stripped to form the source electrode 10 and the drain electrode 11.

(64) Specifically, the sample obtained after the metal evaporation is soaked in acetone for over 3 hours followed by ultrasonicating until the metal in the unexposed region completely peels off to obtain a first metal-removed sample. The first metal-removed sample is placed in a stripping solution at 60 C. for water-bath heating for 15 minutes, and then placed in acetone and isopropanol sequentially in that order for ultrasonic cleaning for 3 minutes, followed by rinsing with ultrapure water for 2 minutes and then drying with nitrogen gas to form the source electrode 10 and the drain electrode 11.

(65) S8, mesa isolation is performed, including following steps S81-S83.

(66) S81, mesa isolation patterns are formed through photolithography.

(67) Specifically, the sample obtained in step S7 is coated with a single-layer anti-etching resist with a thickness of 0.7 m to obtain a coated sample, the exposure is performed on the non-source region of the coated sample through a mask by using a photolithography machine followed by post-baking for 1 minute, and after the post-baking is completed and a sample temperature has dropped to the room temperature, the development is performed to remove the photoresist on the non-source region, completing the photolithography.

(68) S82, dry etching is performed to remove a part of the cap layer 7, a part of the barrier layer 6, a part of the insertion layer 5, a part of the channel region 4 and a part of the buffer layer 3 on the non-source region, to form the mesa isolation.

(69) Specifically, before etching, the sample obtained in step S81 is baked at 100 C. for 1 minute by using a hot plate to enhance the etch resistance of the photoresist. Then, the dry etching is performed using the ICP process to remove the part of the GaN cap layer 7, the part of InAlN barrier layer 6, the part of AlN insertion layer 5, the part of GaN channel region 4 and the part of the GaN buffer layer 3 on the non-source region, with an etching depth of 150 nm, forming the mesa isolation.

(70) S83, the photoresist is removed after etching.

(71) Specifically, the sample obtained in step S82 is placed into acetone, a stripping solution, acetone, and isopropanol sequentially in that order for ultrasonic cleaning to remove the photoresist on the surface, followed by rinsing with ultrapure water and then drying.

(72) S9, the gate electrode 12 is prepared on the arrayed nanochannel structure 71 and in the recesses 72 defined by the arrayed nanochannel structure 71, making the gate electrode 12 disposed between the first n.sup.+-doped material layer 8 and the second n.sup.+-doped material layer 9. The top gate 121 is disposed on the arrayed nanochannel structure 71, and the side gates 122 are disposed in the recesses 72 formed by the arrayed nanochannel structure 71, as shown in FIG. 6L. Step S9 includes following steps S91-S93.

(73) S91, the gate electrode pattern is formed through photolithography on the sample obtained in step S8.

(74) Specifically, a double-layer photoresist is coated on the sample obtained in step S8, with a thickness of lift-off resist at a bottom layer about 0.35 m and a thickness of photoresist at a top layer about 0.56 m; then, the exposure is performed on the gate electrode pattern region through photomask by a photolithography machine followed by post-baking; after the post-baking and a sample temperature has dropped to the room temperature, the development is performed to remove the photoresist on the gate electrode pattern region, thereby completing the photolithography and forming the gate electrode pattern.

(75) S92, a (nickel) Ni/Au metal electrode is deposited via the electron-beam evaporation device.

(76) Specifically, the residual photoresist is removed from the exposed regions by using the plasma resist remover, and then the electron-beam evaporation device is used to sequentially evaporate a Ni layer with a thickness of 45 nm and an Au layer with a thickness of 200 nm.

(77) S93, the metal in the unexposed regions is stripped to form the gate electrode 12.

(78) Specifically, the sample obtained after the metal evaporation is soaked in acetone for over 3 hours followed by ultrasonicating until the metal in the unexposed regions completely peels off to obtain a second metal-removed sample. The second metal-removed sample is placed in a stripping solution at 60 C. for water-bath heating for 15 minutes, and then placed in acetone and isopropanol sequentially in that order for ultrasonic cleaning for 3 minutes, followed by rinsing with ultrapure water for 2 minutes and then drying with nitrogen gas to form the gate electrode 12. The top gate 121 is disposed on the arrayed nanochannel structure 71, and the side gates 122 are disposed in the recesses 72 defined by the arrayed nanochannel structure 71.

(79) S10, metal interconnection is performed to interconnect the source electrode 10, drain electrode 11, and gate electrode 12, including following steps S101-S103.

(80) S101, interconnection patterns are formed through photolithography.

(81) Specifically, the sample obtained in step S9 is coated with photoresist, the exposure is performed on the metal electrode region through the photomask by using the photolithography machine followed by post-baking, and after the post-baking is completed and a sample temperature has dropped to the room temperature, the development is performed to remove the photoresist on the exposed region, completing the photolithography.

(82) S102, Ti/Au metal electrodes are deposited via the electron-beam evaporation device.

(83) Specifically, the residual photoresist is removed from the exposed region by using the plasma resist remover and then the electron-beam evaporation device is used to sequentially evaporate a Ti layer with a thickness of 45 nm and an Au layer with a thickness of 200 nm.

(84) S103, the metal in the unexposed region is stripped to form the metal interconnection structure.

(85) Specifically, the sample obtained after the metal evaporation is soaked in acetone for over 3 hours followed by ultrasonicating until the metal in the unexposed region completely peels off, with retained metal forming the metal interconnection structure. The sample with the metal interconnection structure is placed in a stripping solution at 60 C. for water-bath heating for 15 minutes, and then placed in acetone and isopropanol for ultrasonic cleaning for 3 minutes, followed by rinsing with ultrapure water for 2 minutes and then drying with nitrogen gas to complete the manufacturing of the nanochannel GaN-based device.

(86) In the manufacturing method of the nanochannel GaN-based device of the embodiments, the mask layer 70 is grown before the growth of the n.sup.+ material layers. Then, the patterns of the ohmic regrowth region and the nanochannels 73 are defined simultaneously, allowing the nanochannel structure and the patterned ohmic contact structure to be formed in one step, which reduces the requirements for photolithography alignment precision, effectively avoids process errors, and simplifies the process.

(87) In the manufacturing method of the embodiments, before removing the mask layer 70 from the device surface, a high etch selectivity SiO.sub.2 mask layer is used as an etch stop layer for dry etching. The n.sup.+ material layers on the arrayed nanochannel structure 71 and within the recesses 72 between the nanochannels 73 are removed by using the Cl-based etching, achieving self-alignment of the nanochannels 73, and reducing the difficulty of photolithography and etching processes.

(88) The above content is a further detailed explanation of the disclosure based on specific illustrated embodiments, and cannot be assumed that the specific implementations of the disclosure are limited to these explanations. For those skilled in the art to which the disclosure belongs, several simple deductions or substitutions can be made without departing from the concept of the disclosure, which should be considered as within the scope of protection of the disclosure.