According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a first insulating member, and a second insulating member. The first to third electrodes extend along a first direction. The third electrode includes a first electrode portion. The first semiconductor member includes Al.sub.x1Ga.sub.1-x1N (0x1<1). The first semiconductor member includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region. The second semiconductor member includes Al.sub.x2Ga.sub.1-x2N (0<x21, x1<x2). The second semiconductor member includes a first semiconductor portion, a second semiconductor portion and a third semiconductor portion. The first insulating member includes a first insulating portion. The second insulating member includes a first insulating region.

A process forms a high electron mobility transistor (HEMT) device with a recessed gate without damaging sensitive areas of the HEMT device. The process utilizes a first epitaxial growth process to grow a first set of layers of the HEMT. The epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. The passivation layer is then patterned to provide a passivation structure at a desired location of the recessed gate electrode. The channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of the passivation structure. The result is that the channel layer and the barrier layer growth around the passivation structure. The passivation structure is then removed, effectively leaving a recess in the channel layer. The gate electrode is then formed in the recess.

A semiconductor device according to embodiments of the present invention is a field-effect transistor including a gate electrode between a source electrode and a drain electrode, wherein carriers travel between the source electrode and the drain electrode, a channel control layer is provided between a channel through with the carriers travel and the gate electrode, a recess is disposed at least in part of a surface in contact with the gate electrode on a source electrode side in the channel control layer, and a part of the gate electrode is filled in the recess.

According to one embodiment, a wafer includes a base, a first layer including Al.sub.z1Ga.sub.1-z1N (0<z1<1), a second layer including Al.sub.z2Ga.sub.1-z2N (0<z2<z1), a third layer including Al.sub.z3Ga.sub.1-z3N (0<z3<z2), and a fourth layer. The first layer is between the base and the fourth layer in a first direction. The second layer is between the first layer and the fourth layer in the first direction. The third layer is between the second layer and the fourth layer in the first direction. The fourth layer includes a plurality of first films including Al.sub.y1Ga.sub.1-y1N (0<y11), and a plurality of second films including Al.sub.y2Ga.sub.1-y2N (0y2<1, y2<y1).

A method of manufacturing a nitride semiconductor device according to one or more embodiments is disclosed that includes forming a first nitride semiconductor layer, forming a second nitride semiconductor layer having a higher carrier concentration than the first nitride semiconductor layer on the first nitride semiconductor layer, forming a third nitride semiconductor layer on the second nitride semiconductor layer, forming a fourth nitride semiconductor layer on the third nitride semiconductor layer, forming a first main electrode electrically connected to the first nitride semiconductor layer, forming a second main electrode electrically connected to the fourth nitride semiconductor layer, and forming a control electrode on the third nitride semiconductor layer via an insulating film. In one or more embodiments, during the forming the second nitride semiconductor layer, the second nitride semiconductor layer is formed with higher carbon concentration than the carbon concentration of the first nitride semiconductor layer.

The disclosure provides a group-III nitride device. The group-III nitride device includes a heterojunction epitaxial wafer and at least one island-shaped electrode. The at least one island-shaped electrode of the group-III nitride device is disposed on the heterojunction epitaxial wafer. Each of the at least one island-shaped electrode includes an interconnection metal layer and at least one island-shaped structural layer. The island-shaped structural layer is covered by the interconnection metal layer and connected to the interconnection metal layer.

A nanochannel GaN-based device includes: a substrate layer, a nucleation layer, a buffer layer, a channel region, an insertion layer, a barrier layer, a cap layer, a first highly n.sup.+-doped material layer, a second n.sup.+-doped material layer, a source electrode, a drain electrode, and a gate electrode. A first arrayed pattern edge is formed on a side of the first n.sup.+-doped material layer facing towards the drain electrode. A second arrayed pattern edge is formed on a side of the second n.sup.+-doped material layer facing towards the source electrode. A part of the channel region, the insertion layer, the barrier layer and the cap layer form an arrayed nanochannel structure between a source electrode and a drain electrode. The first arrayed pattern edge is interdigitated with an end of the arrayed nanochannel structure. The second arrayed pattern edge is interdigitated with another end of the arrayed nanochannel structure.

According to one embodiment, a semiconductor device includes first to third electrodes and semiconductor member. The third electrode includes a first electrode portion. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes Al.sub.x1Ga.sub.1-x1N (0x1<1) and includes carbon. The first semiconductor region includes first to sixth partial regions. A first hydrogen concentration in the sixth partial region is lower than a second hydrogen concentration in the fifth partial region. The second semiconductor region includes Al.sub.x2Ga.sub.1-x2N (x1<x21). The second semiconductor region includes a first semiconductor portion. A direction from the fifth partial region to the first semiconductor portion is along the second direction.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a nitride region, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to sixth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The sixth partial region is between the fifth and second partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion is in contact with the fifth partial region. The nitride region includes a first nitride portion being in contact with the sixth partial region. The first insulating member includes a first insulating region between the third partial region and the first electrode portion.

Variations in characteristics of a device which are caused by buried gate electrodes are suppressed. A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a source electrode; a drain electrode; at least one blind hole reaching an interior of the first nitride semiconductor layer from an upper surface of the second nitride semiconductor layer; a buried gate electrode inside the blind hole; and a gate finger electrode across an upper surface of the buried gate electrode and the upper surface of the second nitride semiconductor layer, wherein a side surface of the blind hole is along a {1 1 0 0} plane of the first nitride semiconductor layer.