METHOD FOR PRODUCING POWER SEMICONDUCTOR DEVICE WITH HEAT DISSIPATING CAPABILITY

Abstract

A method for producing a power semiconductor device with heat dissipating capability includes epitaxially growing a GaN-based buffer layer on a first surface of a sapphire substrate, epitaxially growing a Ga.sub.2O.sub.3 semiconductor layer on the GaN-based buffer layer, forming a source and a drain, a gate dielectric layer, a first gate, an insulator layer, and a metal adhesive layer in sequence, removing part of the metal adhesive layer, the insulator layer, and the gate dielectric layer to expose one of the source and the drain, forming a heat sink which covers the metal adhesive layer, the insulator layer, the gate dielectric layer, and the one of the source and the drain, and conducting a laser lift-off process through a second surface of the sapphire substrate to remove the sapphire substrate and the GaN-based buffer layer.

Claims

1. A method for producing a power semiconductor device with heat dissipating capability, comprising: (a) epitaxially growing a GaN-based buffer layer having a hexagonal crystal structure on a first surface of a sapphire substrate; (b) epitaxially growing a Ga.sub.2O.sub.3 semiconductor layer having a monoclinic crystal structure on said GaN-based buffer layer; (c) forming a metal adhesive layer on said Ga.sub.2O.sub.3 semiconductor layer; (d) conducting a wafer bonding process to form a heat sink on said metal adhesive layer; and (e) conducting a laser lift-off process through a second surface of said sapphire substrate opposite to said first surface of said sapphire substrate to remove said Sapphire substrate and said GaN-based buffer layer, so as to expose a surface of said Ga.sub.2O.sub.3 semiconductor layer opposite to the metal adhesive layer.

2. The method according to claim 1, wherein in step (d), said heat sink is made of a material selected from the group consisting of a silicon wafer, a silicon carbide wafer, an aluminum nitride substrate, and combinations thereof.

3. The method according to claim 1, further comprising: (f) forming a source region and a drain region on two opposite sides of said Ga.sub.2O.sub.3 semiconductor layer; (g) forming a source and a drain that are respectively connected to said source region and said drain region of said Ga.sub.2O.sub.3 semiconductor layer; (h) forming a gate dielectric layer covering said exposed surface of said Ga.sub.2O.sub.3 semiconductor layer, said source, and said drain; (i) forming a first gate on said gate dielectric layer; and (j) forming an insulator layer on said first gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiments with reference to the accompanying drawings, of which:

[0027] FIG. 1 is a schematic sectional view illustrating two -Ga.sub.2O.sub.3 thin-film transistors disclosed in Zhou, H. et al. (2017), supra;

[0028] FIG. 2 is a schematic sectional view illustrating steps (a) to (c) of a first embodiment of a method for producing a power semiconductor device with heat dissipating capability according to the present disclosure;

[0029] FIG. 3 is a schematic sectional view illustrating steps (d) to (e) of the first embodiment;

[0030] FIG. 4 is a schematic sectional view illustrating steps (f) to (g) of the first embodiment;

[0031] FIG. 5 is a schematic sectional view illustrating steps (h) to (i) of the first embodiment;

[0032] FIG. 6 is a schematic sectional view illustrating steps (j) to (k) of the first embodiment;

[0033] FIG. 7 is a schematic sectional view illustrating steps (1) to (n) of the first embodiment;

[0034] FIG. 8 is a schematic sectional view illustrating steps (a) to (b) of a second embodiment of a method for producing a power semiconductor device with heat dissipating capability according to the present disclosure;

[0035] FIG. 9 is a schematic sectional view illustrating steps (c) to (d) of the second embodiment; and

[0036] FIG. 10 is a schematic sectional view illustrating step (e) of the second embodiment.

DETAILED DESCRIPTION

[0037] Referring to FIGS. 2 to 6, a first embodiment of a method for heat dissipation of a power semiconductor device according to the present disclosure includes: [0038] (a) epitaxially growing a GaN-based buffer layer 23 having a hexagonal crystal structure on a first surface 21 of a sapphire substrate 2; [0039] (b) epitaxially growing a Ga.sub.2O.sub.3 semiconductor layer 3 having a monoclinic crystal structure on the GaN-based buffer layer 23; [0040] (c) forming a source region 31 and a drain region 32 on two opposite sides of the Ga.sub.2O.sub.3 semiconductor layer 3; [0041] (d) forming a source S and a drain D that are respectively connected to the source region 31 and the drain region 32 of the Ga.sub.2O.sub.3 semiconductor layer 3; [0042] (e) forming a gate dielectric layer 4 covering the Ga.sub.2O.sub.3 semiconductor layer 3, the source S, and the drain D; [0043] (f) forming a first gate G1 on the gate dielectric layer 4; [0044] (g) forming an insulator layer 5 on the first gate G1; [0045] (h) forming a metal adhesive layer 6 on the insulator layer 5; [0046] (i) removing part of the metal adhesive layer 6, the insulator layer 5, and the gate dielectric layer 4 to expose one of the source S and drain D; [0047] (j) conducting an electroforming process to form a heat sink 7 which covers the metal adhesive layer 6, the insulator layer 5, the gate dielectric layer 4, and the one of the source S and the drain D; and [0048] (k) conducting a laser lift-off process through a second surface 22 of the sapphire substrate 2 opposite to the first surface 21 of the sapphire substrate 2 to remove the sapphire substrate 2 and the GaN-based buffer layer 23, SO as to expose surfaces of the Ga.sub.2O.sub.3 semiconductor layer 3, the source S, and the drain D that are opposite to the gate dielectric layer 4.

[0049] The details of the steps are described below.

[0050] In step (a) of this embodiment, the sapphire substrate 2 has a thermal conductivity (k) of about W/m.Math.K.

[0051] In step (a) of this embodiment, the GaN-based buffer layer 23 is epitaxially grown on the first surface 21 of the sapphire substrate 2 through metal-organic chemical vapor deposition MOCVD using trimethylgallium (TMG, Ga(CH.sub.3).sub.3) and N.sub.2 as precursors.

[0052] In step (b) of this embodiment, the Ga.sub.2O.sub.3 semiconductor layer 3 is epitaxially grown on the GaN-based buffer layer 23 through MOCVD using TMG and O.sub.2 as precursors.

[0053] In step (c) of this embodiment, the source region 31 and the drain region 32 may be formed by conducting a patterning process to remove part of the Ga.sub.2O.sub.3 semiconductor layer 3 and expose the GaN-based buffer layer 23. Optionally, after the patterning process, the two opposite sides of the Ga.sub.2O.sub.3 semiconductor layer 3 may be further subjected to an ion implantation process to form a high doping concentration.

[0054] In step (d) of this embodiment, each of the source S and the drain D is a Ti/Al/Au contact electrode made by sputtering.

[0055] In step (e) of this embodiment, the gate dielectric layer 4 is made of Al.sub.2O.sub.3.

[0056] In step (f) of this embodiment, the first gate G1 is a Ni/Au gate made by sputtering.

[0057] In step (g) of this embodiment, the insulator layer 5 is formed on the first gate G1 to cover the first gate G1 and the gate dielectric layer 4.

[0058] In step (i) of this embodiment, after removing the part of the metal adhesive layer 6, the insulator layer 5, and the gate dielectric layer 4, the drain D is exposed.

[0059] The heat sink 7 may be made of a metal selected from the group consisting of silver (Ag), copper (Cu), gold (Au), aluminum (Al), sodium (Na), molybdenum (Mo), tungsten (W), zinc (Zn), nickel (Ni), and combinations thereof. For instance, the heat sink 7 is made of copper (Cu) having a thermal conductivity (K) of 401 W/m.Math.K.

[0060] In this embodiment, referring to FIG. 7, the production method may further include: [0061] (l) forming an oxide layer 8 on the exposed surface of the Ga.sub.2O.sub.3 semiconductor layer 3; [0062] (m) forming an electrode pad 9 on the exposed surface of a respective one of the source S and the drain D; and [0063] (n) forming a second gate G2 on the oxide layer 8, the second gate G2 being configured to be a field plate.

[0064] The second gate G2 may be made of Ti/Au to reduce hot electrons and the leakage current effect.

[0065] In this embodiment, since the Ga.sub.2O.sub.3 semiconductor layer 3 is epitaxially grown, through MOCVD, on the GaN-based buffer layer 23 that is grown on the first surface 21 of the sapphire substrate 2, the lattice mismatch between the GaN-based buffer layer 23 having a hexagonal crystal structure and the Ga.sub.2O.sub.3 semiconductor layer 3 having a monoclinic crystal structure is low. By virtue of the epitaxial growth process, the threading dislocation density of the Ga.sub.2O.sub.3 semiconductor layer 3 can be reduced, so that the Ga.sub.2O.sub.3 semiconductor layer 3 has excellent epitaxial quality.

[0066] Moreover, the sapphire substrate 2 having a thermal conductivity (k) of about 40 W/m.Math.K is removed by a laser lift-off process, and copper (Cu) having a thermal conductivity (k) of 401 W/m.Math.K is used to form the heat sink 7 above the Ga.sub.2O.sub.3 semiconductor layer 3, thereby further reducing the thermal resistance and improving the heat dissipation effect.

[0067] In addition, referring to FIGS. 8 to 10, a second embodiment of the production method according to the present disclosure includes: [0068] (a) epitaxially growing a GaN-based buffer layer 23 having a hexagonal crystal structure on a first surface 21 of a sapphire substrate 2; [0069] (b) epitaxially growing a Ga.sub.2O.sub.3 semiconductor layer 3 having a monoclinic crystal structure on the GaN-based buffer layer 23; [0070] (c) forming a metal adhesive layer 6 on the Ga.sub.2O.sub.3 semiconductor layer 3; [0071] (d) conducting a wafer bonding process to form a heat sink 7 on the metal adhesive layer 6; and [0072] (e) conducting a laser lift-off process to remove the sapphire substrate 2 and the GaN-based buffer layer 23, so as to expose a surface of the Ga.sub.2O.sub.3 semiconductor layer 3 opposite to the metal adhesive layer.

[0073] In the second embodiment, the heat sink 7 may be made of a material selected from the group consisting of a silicon wafer, a silicon carbide wafer, an aluminum nitride substrate, and combinations thereof.

[0074] In the second embodiment, the production method may further include: [0075] (f) forming a source region 31 and a drain region 32 on two opposite sides of the Ga.sub.2O.sub.3 semiconductor layer 3; [0076] (g) forming a source S and a drain D respectively on the source region 31 and the drain region 32 of the Ga.sub.2O.sub.3 semiconductor layer 3, so that the source S and the drain D are respectively connected to the opposite sides of the Ga.sub.2O.sub.3 semiconductor layer 3; [0077] (h) forming a gate dielectric layer 4 covering the exposed surface of the Ga.sub.2O.sub.3 semiconductor layer 3, the source S, and the drain D; [0078] (i) forming a first gate G1 on the gate dielectric layer 4; and [0079] (j) forming an insulator layer 5 on the first gate G1.

[0080] The formation of the source region 31 and the drain region 32, the formation of the source S and the drain D, and the formation of the gate dielectric layer 4, the first gate G1, and the insulator layer 5 in the second embodiment may be similar to those described for the first embodiment.

[0081] In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment(s). It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to one embodiment, an embodiment, an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.

[0082] While the disclosure has been described in connection with what are considered the exemplary embodiments, it is understood that this disclosure is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation SO as to encompass all such modifications and equivalent arrangements.