Approach for an Area-Efficient and Scalable CMOS Performance Based on Advanced Silicon-On-Insulator (SOI), Silicon-On-Sapphire (SOS) and Silicon-On-Nothing (SON) Technologies

Abstract

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOL SOS or SON technologies. The design methodology depends on new proprietaries device architectures that are also being claimed in this patent and that allow the implementations of the design equations in our methodology.

Claims

1. A single-leg Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI-MOS) compromising; a highly P-doped pocket (P_Pocket) in Front-Silicon under the Gate that interfaces on one side the full thickness of the MOS Body along the full peripheral width of the device structure while it junctions the full thickness of the Source region on its opposite side, this P_doped pocket has a higher doping relative to P_Body and is wired to Body-Tied-Source (BTS) region(s), this higher doping can be many orders of magnitude higher; this arrangement imposes a hard barrier for an Impact-Ionizations current in the P_body to laterally diffuse through the Body/Source junction and forces it to conduct instead through the P_Pocket along the wider peripheral width of the device structure to configuration of BTS that connects to the P_Pocket, this BTS configuration can be specifically designed to split the Impact-Ionizations current (II-current) into parallel paths, increasing therefore the overall equivalent conductance that the Impact-Ionizations current sees between the P_Body and BTS; the lateral dimensions of the P_Pocket can be made to be relatively wide so to significantly increase its conductance; the BTS stripe(s) can have corner-rounded dimensions that alleviate current-crowding of the II-current as it converges to BTS from P_Pocket or can have simpler rectangular shapes; higher Impact-Ionizations current (II-current) resulting from larger device peripheral width of this single-leg MOS device structures requires proportional scale-up of the equivalent conductance that the Impact-ionizations current sees between the P_Body and BTS; this is accomplished through insertion of additional BTS stripes; for given effective-Gate-Width (WGeff), Bipolar leakage, and operating bias, the number of its BTS stripes (N) and the spacing(s) between them conform exactly or similarly to the model, $\begin{array}{c}\mathrm{•II}-\mathrm{current}=I_{\mathrm{Bipolar}}+\mathrm{Vdrop}\times \left(N\right)\times \left(q\times {\mu }_h\times \mathrm{NA}\right)\times \frac{\mathrm{Wp}\times \left(\mathrm{tsi}-\mathrm{Depl}.Math..Math.\max \right)\times 4}{\mathrm{SPAC}}\\ \mathrm{•WGeff}=N\times \mathrm{SPAC}\end{array}$ when the both edges of the device peripheral Width on the Source side are Source regions; they can also conform to the model, $\begin{array}{c}\mathrm{•II}-\mathrm{current}=I_{\mathrm{Bipolar}}+\mathrm{Vdrop}\times \left(N-1\right)\times \left(q\times {\mu }_h\times \mathrm{NA}\right)\times \frac{\mathrm{Wp}\times \left(\mathrm{tsi}-\mathrm{Depl}.Math..Math.\max \right)\times 4}{\mathrm{SPAC}}\\ \mathrm{•WGeff}=\left(N-1\right)\times \mathrm{SPAC}\end{array}$ when the both edges of the device peripheral Width on the Source side are Body-Tied-Source stripes; the claim extends to analogous PMOS structures and layouts; the claim extends to devices fabricated on any buried dielectric beside the Silicon-dioxide, this includes Silicon-On-Sapphire (SOS), Silicon-On-Nothing, and all the insulating substrates (e.g. flexible organic substrates); the claim extends to multi-legs (or multi-fingers) device structures in which at least one leg (or one finger) is composed of the claimed proprietary SOI-MOS structures that incorporate this unique wiring of P_Pocket to a configuration of Body-Tied-Source that increases or maximizes the equivalent conductance that the Impact-Ionization current sees between the single-leg device Body and BTS; the claim extends to any and all Integrated-Circuits that use these single-leg Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI-MOS) structures that incorporate this unique wiring of P_Pocket to a configuration of Body-Tied-Source that increases or maximizes the equivalent conductance that the Impact-Ionization current sees between the device Body and BTS.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0017] FIG. 1: Comparative “drawn” schematics illustrating the comparison between one non-optimal layout of an SOI-NMOS (left-hand side) versus an optimized layout design (right-hand side) of a same device. The non-optimal design used extra unneeded BTS area to meet targeted electric specifications with a fully suppressed FBE; the optimized design used on the other hand minimum possible BTS area for an equal suppression of FBE at same electric specifications and same total peripheral layout area. The WGeff in the optimized design is higher and so are its drive current and speed.

[0018] FIG. 2 A: Top view schematic of a proprietary single-legged SOI-NMOS device architecture that is being claimed in this patent. It ensures highest possible conductance between P_Body and BTS that the Impact-Ionizations current (II-current) sees for given device periphery layout. This highest conductance is realized through the implantation of very highly conductive channel or canal (P_Pocket) that interfaces on its one side the full peripheral width of the device structure while it junctions the Source on its opposite side. This higher doping of this pocket (P_Pocket) relative to P_Body imposes hard barrier for II-current in P_Body to laterally diffuse through this junction and forces it to split instead into paralleled paths and conduct to the narrow BTS stripe through this P_Pocket along the much wider WG. These paralleled paths for II-current increase the equivalent conductance between P_Body and BTS for given WG. A narrow BTS stripe width (WB) is essential for area-efficiency as the Silicon volume consumed by BTS does not contribute to device current. Smooth corner-rounding of the BTS edges can suppress current-crowding and boost the equivalent conductance. The BTS stripes can also be fully rectangular as in the FIG. 1. Gate, its dielectric, and Spacers regions are not shown. Gate and its dielectric are shown in the side views of FIG. 3 A, FIG. 3 B, and FIG. 3 C that further describe this same singled-leg SOI MOS device structure. The “LG” symbolizes the Gate-Length.

[0019] FIG. 2 B: Schematic illustrating the conductive path for Impact-Ionizations current in the device structure of FIG. 2 A.

[0020] FIG. 3 A: “Cartoon” schematic showing the corresponding Front view of the same claimed proprietary architecture of FIG. 2 A based on either the SOI or the SOS. The spacers on both lateral ends of the Gate are not being shown; they can be same as in any standard CMOS process. (Back view is similar).

[0021] FIG. 3 B: “Cartoon” schematic showing the Side view from the Source side of the same claimed architecture of FIG. 2 A based on either the SOI or the SOS.

[0022] FIG. 3 C: “Cartoon” schematic showing the side view from the Drain side of the same claimed proprietary architecture of FIG. 2 A based on either the SOI or the SOS.

[0023] FIG. 4: “Cartoon” schematic showing the corresponding front view of the claimed proprietary architecture of FIG. 2 A, but based on SON, (the back view is similar). Its side views are similar to those of FIG. 3 B and FIG. 3 C, but with the “BOX/SOS” layer substituted with N+ Source and N+ Drain. Similarly, Spacers on both lateral ends of the Gate are not shown; they can be same as in any standard CMOS process.

[0024] FIG. 5: An illustrative top-view layout of a larger-periphery version of the single-legged SOI-NMOS device structure of FIG. 2 A. It uses 4 BTS stripes. Its “effective” Gate width is: 4×SPAC. Gate, its dielectric, and Spacers regions are not shown.

[0025] FIG. 6 A: Top view schematic of another proprietary single-legged SOI-NMOS device that is also being claimed in this patent. It similarly splits the Impact-Ionizations current through P_Pocket into two paralleled paths that ensure similar highest conductance that this Impact-Ionizations (II-current) sees between the P_Body and BTS for given WG. Its minor drawback compared to the layout of FIG. 2 A is that it requires one additional BTS stripe for a same WGeff. Gate, its dielectric, and Spacers regions are not shown. Gate and its dielectric are shown in the side views of FIG. 7 A and FIG. 7 B.

[0026] FIG. 6 B: Schematic illustrating the conductive path for Impact-Ionizations current in the device structure of FIG. 6 A.

[0027] FIG. 7 A: “Cartoon” schematic showing the corresponding Front view of the same claimed proprietary architecture of FIG. 6 A based on either the SOI or the SOS. The spacers on both lateral ends of the Gate are not being shown; they can be same as in any standard CMOS process. (Back view is similar).

[0028] FIG. 7 B: “Cartoon” schematic showing the Side view from the Source side of the same claimed architecture of FIG. 6 A based on either the SOI or the SOS. (The side view from the Drain side is same as that of FIG. 3 C).

[0029] FIG. 8: “Cartoon” schematic showing the corresponding front view of the claimed proprietary architecture of FIG. 6 A, but based on SON (the back view is similar). Its side views are similar to those of FIG. 7 B and FIG. 3 C, but with the “BOX/SOS” substituted N+ Source and N+ Drain. Spacers on both lateral ends of the Gate are not shown; they can be same as in any standard CMOS process.

[0030] FIG. 9: An illustrative top-view layout of a larger-periphery version of the single-legged SOI-NMOS device structure of FIG. 6 A. It uses 4 BTS stripes. Its “effective” Gate width is: (4-1)×SPAC=3×SPAC. Gate, its dielectric, and Spacers regions are not shown.

[0031] FIG. 10: A 3D TCAD simulation illustrating the impact of extra summative BTS areas on the WGeff in a large-periphery 1-leg FD-SOI NMOS. As more BTS area gets consumed within the total layout periphery of the device, the conductive path for electron current gets reduced, and therefore the effective Gate-Width (WGeff) of the device is also reduced. A total of eleven BTS stripes were utilized in that simulation.

[0032] Key concept in our guided design approach is that it maintains for the targeted (desired) electric specifications such summative total area consumed by BTS to a very minimum while effectively suppressing the FBE.

[0033] FIG. 11: A 3D TCAD simulation illustrating the parasitic Bipolar latch-up in an un-optimized large-periphery 1-leg FD-SOI NMOS based on the device structure of FIG. 6 A. Shown is LOG.sub.10 of the Recombination Rate. As shown, Diffusion current is strongest toward the center between 2 BTS where the voltage-drop in P_Pocket due to the conducting Holes from Impact-ionization is highest, and so is the barrier lowering.

[0034] FIG. 12: Simulation of the Body potential in a fully optimized large-periphery 1-leg FD-SOI NMOS. It exhibited less than a 0.1V throughout its P_Body. The device was optimized in the back-accumulation mode (with an applied negative bias to its Back-Gate, in addition to the positive bias for inversion at the Front-Gate). These boosted further the conductance that the Impact-Ionizations current sees between the P_Body and the BTS. WB=0.5 μm.

[0035] FIG. 13: Measured and simulated Current-Voltage transfer curves of FD-SOI NMOS devices (WGeff=2 μm; LG=0.35 μm; VD=3.3V); Box=0.5 μm; CFox-10 nm; tsi=35 nm; WB=μm). Clearly shown is the Bipolar effect in a device that failed to maintain low voltage drop throughout its P_Pocket. The optimal device on the other hand effectively suppressed the Bipolar effect.

[0036] FIG. 14: Measured and simulated Subthreshold-Slope (SS), from 3D TCAD, in our optimized FD SOI NMOS (WGeff=2 μm; LG=0.35 μm; VDS=3.3V; Box=0.5 μm; tox-10 nm; tsi=35 nm). Its relatively high SS of 98 mV/Dec is caused from the effect of its highly doped P_Pocket. (Typical values for SS are: 65-80 mV/Dec with FD SOI; 80-120 mV/Dec with PD SOI; and ≧120 mV/Dec with bulk Si substrate).

DETAILED DESCRIPTION OF THE INVENTION

[0037] A top-view of such device layout is depicted in FIG. 2 A. Further schematics describing its structures are shown in FIG. 3 A, FIG. 3 B, and FIG. 3 C. The P_Pocket extends from the Source into the “effective” Gate-Length of the device (LGeff) a distance: Wp that is a relatively small fraction of LGeff so to ensure the P_Pocket is conductive enough and with no or little penalty on the device VT. A tighter or a more loose constraint on Wp may always be set for the specific application. As is shown with the dashed-arrows in FIG. 2 A, the device structure splits the II-current that generates around its Drain's edge into two equal magnitudes that converge through separate paths to the BTS while conducting in P_Pocket alongside the Gate-width of the structure. FIG. 2 B shows an equivalent circuit diagram depicting the flow of Impact-Ionizations current (II-current) to the BTS. The dashed-rectangle in FIG. 2 A shows region within the device structure that does not conduct device current, and no consequent Impact-Ionizations occur either within it in following the II-current model described by X. Gu et al.:

[00001]$\mathrm{II}-\mathrm{current}=I_{\mathrm{Device}}\times \left[\frac{\alpha }{\Omega }\times \left(\mathrm{VD}-\Gamma \times \mathrm{Vknee}\right)\times e^{-\frac{\mathrm{lm}\times \Omega }{\mathrm{VD}-\Gamma \times \mathrm{Vknee}}}\right].Math.\alpha ,\Omega ,\mathrm{lm}.Math..Math.\mathrm{and}.Math..Math.\Gamma .Math..Math.\mathrm{are}$

parametrization constants. A lateral device current must conduct through this dashed-rectangle region of FIG. 2 A to kick Impact-Ionizations and it does not. This also reduces the portion from WG that conducts device current to WGeff=2×N×SPAC/2=SPAC (N is the number of narrow stripes used for BTS. N=1 in FIG. 2 A). WB is the width of the very narrow BTS stripe(s) that interface(s) the P_Body along the WG. As is intuitive from the above equation, the II-current does increase with WGeff since the I.sub.Device increases with WGeff. Part of the II-current conducts through this P_Pocket while its other part leaks through the lateral junction between Body and Source. The corresponding equation for the currents-balance from Kirchoff-Current-Law (KCL) is:

[00002]$\frac{\mathrm{II}-\mathrm{current}}{2\times N}=\frac{I_{\mathrm{Bipolar}}\left(\mathrm{Vdrop}\right)}{2\times N}+\mathrm{Vdrop}\times {\sigma }_{P.Math.\_.Math.\mathrm{Pocket}}.$

Vdrop is the voltage-drop in P_Pocket from the portion of II-current that conducts through it. σ.sub.P.sub._.sub.Pocket is the conductance of P_Pocket on each side of the BTS. Its analytic model from simple device Physics is:

[00003]$\begin{array}{cc}{\sigma }_{P.Math.\_.Math.\mathrm{Pocket}}=\frac{1}{\rho }\times \frac{\mathrm{area}}{\mathrm{length}}=\left(q\times {\mu }_h\times \mathrm{NA}\right)\times \frac{\mathrm{Wp}\times \left(\mathrm{tsi}-\mathrm{Depl}.Math..Math.\max \right)\times 2}{\mathrm{SPAC}}& \left(1\right)\end{array}$

q is the electron-charge unit, tsi is the thickness of the Silicon film, μ.sub.h is the Hole-Mobility in P_Pocket, and NA is the doping concentration in this P_Pocket. The II-current splits into two parallel paths to BTS and scales the equivalent conductance between P_Body and BTS to:

2×N×σ.sub.P.sub._.sub.Pocket=2×σ.sub.P.sub._.sub.Pocket.

[0038] The above expression for σ.sub.P.sub._.sub.Pocket does not account to the effect of lateral depletion in P_Pocket since a lightly doped region at Source (N−) absorbs most of this junction depletion. The expression still accounts nonetheless to the impact from the transversal depletion in P_Pocket while assuming the extreme scenario that P_Pocket strongly inverts. Expression for this transversal depletion is:

[00004]$\mathrm{Depl}.Math..Math.\max =2\times \sqrt{\frac{\mathrm{.Math.}.Math..Math.\mathrm{tsi}\times \varphi .Math..Math.p}{q\times \mathrm{NA}}},\mathrm{with}.Math..Math.\varphi .Math..Math.p=\mathrm{vth}\times \ln \left(\frac{\mathrm{NA}}{\mathrm{ni}}\right).Math.\mathrm{.Math.tsi}$

is the electric-dielectric constant of Silicon, and ni is the intrinsic carrier concentration of Silicon.

[0039] The expression for the KCL balance for currents can be rewritten as:

II-current=I.sub.Bipolar(Vdrop)+Vdrop×(2×N)×σ.sub.P.sub._.sub.Pocket  (2)

[0040] In substituting equation (1) into equation (2) it is obtained:

[00005]$\mathrm{II}-\mathrm{current}=I_{\mathrm{Biploar}}\left(\mathrm{Vdrop}\right)+\mathrm{Vdrop}\times \left(2\times N\right)\times \left(q\times {\mu }_h\times \mathrm{NA}\right)\times \frac{\mathrm{Wp}\times \left(\mathrm{tsi}-\mathrm{Depl}.Math..Math.\max \right)\times 2}{\mathrm{SPAC}}$

[0041] Equation (3) states that an equivalent conductance that the II-current sees from the P_Body of the device of FIG. 2 A is: (2×N)×σ.sub.P.sub._.sub.Pocket=2×σ.sub.P.sub._.sub.Pocket. This compares to a conductance of:

[00006]$\frac{{\sigma }_{\mathrm{P\_Pocket}}}{2}$

if the BTS stripe was connected instead at the very edge of the WG in FIG. 2 A and with an exact same WGeff=SPAC. That is an increase by factor of 4 for same WGeff, simply from optimum positioning same BTS stripe along the WG.

[0042] Due to the finite magnitude of σ.sub.P.sub._.sub.Pocket for any given values for Wp, NA, μ.sub.h, and tsi, the structure of FIG. 2 A (with N=1) cannot manage the high magnitudes of II-current from devices with very large peripheries while it still suppresses the parasitic Bipolar current. This is especially true when high VD is applied as this will further amplify the II-current. Significant Bipolar leakage will then occur. The fix is to insert more BTS stripes to scale-up the equivalent conductance between the P_Body and BTS. This will further split the II-current among more paralleled BTS stripes and scales the equivalent conductance that the II-current sees between P_Body and BTS in proportion to (2×N)×σ.sub.P.sub._.sub.Pocket. The II-current will then split by factor: 2×N and each portion of it sees a conductance σ.sub.P.sub._.sub.Pocket, and same

[00007]$\frac{1}{2\times N}$

fraction from the total Bipolar leakage. A schematic for such large-periphery structure is shown in FIG. 5. With N=4, and WGeff=4×SPAC. Equivalent conductance seen from P_Body scales to 2×N×σ.sub.P.sub._.sub.Pocket=8×σ.sub.P.sub._.sub.Pocket.

[0043] Key criterion is to maintain lowest number of BTS stripes for fixed magnitudes of WGeff, WB, tsi, Wp, and for tolerated preset magnitude for the Bipolar leakage due to II-Current at the given bias (a rule-of-thumb is to design for Bipolar leakage one to two order(s) of magnitude lower than the I.sub.Device). This is what ensures that for given bias, best area-efficiency of layout is achieved (such that WGeff is closest to WG) and with adequate suppression of the device built-in parasitic Bipolar current.

[0044] The general procedure for the design is: [0045] 1—The required WGeff for the device to deliver its operating current target (its desired I.sub.Device current) at its VT and bias can be extracted from any DC model that models the MOS device current function of VT. One possible model is that described by Kwyro Lee, Michael Shur, Tor A. Fjeldly, and Trond Ytterdal, Semiconductor Device Modeling for VLSI, New Jersey: Prentice Hall, pp. 238-256, 1993. [0046] 2—Value for the I.sub.Bipolar(Vdrop) is affixed to magnitude significantly lower than the I.sub.Device (e.g. generally one to two order(s) of magnitude lower, but may still be even lower). An accurate model for the Bipolar current is crucial to extract the corresponding Vdrop magnitude to this affixed value of I.sub.Bipolar(Vdrop). One possible model can be that described by Ben G. Streetman, Solid State Electronic Devices, 4.sup.th ed. New Jersey: Prentice Hall, pp. 244-247, 1995. [0047] 3—For the targeted (or the desired) values for VD and I.sub.Device the II-current is extracted for its WGeff from any accurate model that models the Impact-Ionizations current (e.g. the model described by X. Gu et al).

[0048] For the accurate extractions of all of WGeff, Vdrop, and II-current at the targeted (or the desired) VD and I.sub.Device, the utmost accurate parametrization constants reflecting on the specific fabrication-process and layout peripheries must be utilized in the selected models that are used to model the DC MOS currents, the Bipolar leakage, and the Impact-Ionizations.

[0049] Specifically-built test-structures on test-chips (or test-vehicles) are utilized for the most accurate extractions of the parametrization constants for the models prior to using these models in the steps 1, 2 and 3 above. Test-structures can also used to extract the μ.sub.h.

[0050] The number of required stripes for BTS, that is N and the required spacing(s) between these stripes are then extracted from the system-model below:

[00008]$\begin{array}{cc}\mathrm{•II}-\mathrm{current}=I_{\mathrm{Bipolar}}+\mathrm{Vdrop}\times \left(2\times N\right)\times \left(q\times {\mu }_h\times \mathrm{NA}\right)\times \frac{\mathrm{Wp}\times \left(\mathrm{tsi}-\mathrm{Depl}.Math..Math.\max \right)\times 2}{\mathrm{SPAC}}& \left(4\right)\\ \mathrm{•WGeff}=\left(2\times N\right)\times \mathrm{SPAC}/2=N\times \mathrm{SPAC}& \left(5\right)\end{array}$

[0051] Daghighi et al. recognized through his work on PD-SOI MOS: Arash Daghighi, Mohamed Osman, and Mohamed A. Imam, “An area efficient body contact for low and high voltage SOI MOSFET devices”, Solid-State Electronics, vol. 52, iss. 2, pp. 196-204, February 2008, that the insertion of many more BTS stripes reduces the Body potential caused from Impact-ionizations and can alleviate the FBE and the Bipolar latch-up, which may allow a degree of scale-up for larger WGeff s and currents. He failed to realize though that the added incorporation of very highly conductive channel/canal in the device Body, along its entire width, and that junctions the Source and ties all the BTS stripes together can dramatically reduce this Body potential to permit significant reduction of the number of BTS stripes required to maintain adequate suppression of the Bipolar effects for same bias. This would consequently result in larger WGeff and higher device current for same total peripheral footprint of layout. Such highly conductive channel/canal (P_Pocket) is doped higher than the Body and extends laterally into it. Daghighi et al. did not realize either that his same device layout is not effective for the FD-SOI MOS as the high II-current will opt to shorten to the Source through an already-lowered lateral barrier rather than to conduct to BTS through the higher resistivity of the fully-depleted Body.

[0052] Design that can be closest to the new innovative device structures that are introduced in this patent is that of U.S. Pat. No. 5,185,280 (Theodore W. Houston et al., U.S. Ser. No. 00/518,5280A, FIG. 4 & FIG. 4a in U.S. Ser. No. 00/518,5280A). This design accounts to the advantage of tying the BTS implant to highly doped Halo pocket, but fails to realize that for given WG there exists optimal configuration for BTS that gives highest area-efficiency (maximizes WGeff for same WG). Furthermore, the highly doped pocket (having same dopant as Body) of the device design in that U.S. Ser. No. 00/518,5280 patent does not fully separate the entire Body region from the lightly doped Source region. Consequently, the area for this Pocket is low and so is its conductance, especially when thin silicon film is used (small tsi). This may require more BTS stripes to suppress parasitic Bipolar leakage for same bias (hence larger WG periphery for same device current). Also the extrinsic Source resistance that the device current of patent U.S. Ser. No. 00/518,5280 sees is high.

[0053] Another proprietary device structure for singled-legged SOI-NMOS is shown in FIG. 6A, FIG. 7 A, and FIG. 7 B. It results in same equivalent high conductance between P_Body and BTS as that of FIG. 2 A, but with a different style of connecting P_Pocket to BTS. It is less area-efficient for same WG as it uses one additional BTS stripe. FIG. 9 shows a scaled-up version of its structure in which 4 BTS stripes are used (N=4. Similarly, its KCL current balance and scaling conform to the system model:

[00009]$\begin{array}{cc}\mathrm{•II}-\mathrm{current}=I_{\mathrm{Bipolar}}+\mathrm{Vdrop}\times \left(N-1\right)\times \left(q\times {\mu }_h\times \mathrm{NA}\right)\times \frac{\mathrm{Wp}\times \left(\mathrm{tsi}-\mathrm{Depl}.Math..Math.\max \right)\times 4}{\mathrm{SPAC}}& \left(6\right)\\ \mathrm{•WGeff}=\left(N-1\right)\times \mathrm{SPAC}& \left(7\right)\end{array}$

[0054] Note that for very large N, Equation (6) approaches that of Equation (4), and Equation (7) approaches that of Equation (5).

[0055] Table 1 displays device parameters for the optimization performed on the device structure of FIG. 12 following the general design procedure described in this section. Table 2 shows the parameterization constants that were extracted from the specifically-built test-structures, and the design equations used from models

[0056] Additional models were used to account to the long-channel and the short-channel VTs. Model for the long-channel VT was taken from the work of Hyung-Kyu, student member, IEEE, and Jerry G. Fossum, Fellow, IEEE, “Threshold voltage of thin-film Silicon-On-Insulator (SOI) MOSFET's, IEEE Trans. Electron Devices, vol. 30, no. 10, pp. 1244-1251, October 1983. And, the model to correct this VT for short-channel effects independently from the effect of II-current was derived in this work.

TABLE-US-00001 TABLE 1 Process Parameters and the design optimization on FD-SOI MOSFET Value Processparameter Tsi, (nm) 35   Tox, (nm) 9   BOX, (nm) 500    LGeff, (nm) 350    Target Bias VGS (V) 0.8 VD (V) 3.3 Optimization Wp (nm) 24   NB (cm.sup.−3) 4 × 10.sup.17 NA (cm.sup.−3) 8 × 10.sup.19 N- (cm.sup.−3) 5 × 10.sup.19 WGeff (μm) 9.5 VGB (V) −0.8  SPAC (μm) & N Extracted to meet target Bipolar leakage

TABLE-US-00002 TABLE 2 Design Equations and the “equation”-based design flow for optimization Design Example  // Sec. I - CONSTANTS: Electric dielectric constant in space. εo = 8.85 × 10.sup.−12 (F/m) Relative dielectric constant of Silicon. εsi = 11.68 relative dielectric constant of Silicon Dioxide. εox = 3.9 Default (or extracted) value for electron channel mobility. μn = 1350 × 10.sup.−4 (m.sup.2/(V.s)) Default (or extracted) value for Hole mobility. μh = 480 × 10.sup.−4 (m.sup.2/(V.s)) Default value for electron Saturation-Velocity. vsat = 10.sup.5 (m/s) Default values for parameters defining impact-ionization current. [00010]$\frac{\alpha }{\Omega }=4\times {10}^5.Math.\left(1/V\right)$ lm × Ω = 50 Γ = 0.5 Workfunction at the front Gate (default or extracted). φ.sub.MS.sup.f = −0.75 (V) Workfunction at the Gate relative to higher doped P_Pocket (default or extracted) φ.sub.MS,Pocket.sup.f = −0.9 (V) Workfunction at the back gate (default or extracted). φ.sub.MS.sup.b = 0.5 (V) Intrinsic carrier concentration of Silicon. ni = 1.5 × 10.sup.16 (m.sup.−3) Thermal-Voltage at room temperature. vth = 26 × 10.sup.−3 (V) Electron charge unit. q = 1.6 × 10.sup.−19 (C) Correction factor accounting to charging in BOX. Corr = 0.8  // Sec. II -Technology-specific process parameters and dimensions: Physical thickness of front Silicon film. tsi = 35 × 10.sup.−9 (m) Physical thickness of BOX. BOX = 0.5 × 10.sup.−6 (m) Physical thickness of front oxide. tox = 9 × 10.sup.−9 (m) Effective Gate length or channel length. LGeff = 0.35 × 10.sup.−6 (m) Effective Gate width. WGeff = 9.5 × 10.sup.−6 (m) Body doping concentration Nb = 4 × 10.sup.17 (cm.sup.−3) Pocket doping concentration NA = 8 × 10.sup.19 (cm.sup.−3) LDD doping concentration N.sup.− = 5 × 10.sup.19 (cm−3) Lateral width of P_ Pocket Wp = 24 (nm) Constant capturing DIBL effect between technology nodes. γ = 1.5  // Sec. III - Design Equations for Calculation of Front threshold-voltage independent of short-channel effects. (Source: HYUNG-KYU et al., “Threshold voltage of thin-film Silicon-On-Insulator (SOI) MOSFET's, IEEE Trans. Elec. Dev., vol. 30, no. 10, pp. 1244-1251, October 1983).   Case-1: The Back-Surface of Front-Silicon film that interfaces the BOX is   depleted: [00011]$\mathrm{VTHO}={\phi }_{\mathrm{MS}}^f-\frac{q\times \mathrm{Qf}.Math.f}{\mathrm{CFox}}+2.Math.\phi .Math..Math.B+\frac{q\times \mathrm{NB}\times \mathrm{tsi}}{2\times \mathrm{CFox}}+\frac{\mathrm{.Math.o}\times \mathrm{.Math.si}}{\mathrm{tsi}\times \mathrm{CFox}}\times \left(2.Math.\mathrm{\phi B}-\mathrm{\Psi sb}\right)$ Eq. 1 [00012]$\phi .Math..Math.B=\mathrm{vth}\times \ln \left(\frac{\mathrm{Nb}}{\mathrm{ni}}\right)$ [00013]$\mathrm{CFox}=\frac{\mathrm{.Math.o}\times \mathrm{.Math.ox}}{\mathrm{tox}}$ Eq. 2 [00014]${\Psi }_{\mathrm{sb}}=\frac{\mathrm{CBOX}}{\mathrm{CBOX}+\mathrm{Cb}}\times \left(V_{\mathrm{GB}}-V_{\mathrm{GB},\mathrm{acc}}\right)$ Eq. 3 [00015]$\mathrm{Cb}=\frac{\mathrm{.Math.o}\times \mathrm{.Math.si}}{\mathrm{tsi}}$ Eq. 4 [00016]$\mathrm{CBOX}=\frac{\mathrm{.Math.o}\times \mathrm{.Math.ox}}{\mathrm{Corr}\times \mathrm{BOX}}$ Eq. 5 [00017]$V_{\mathrm{GB},\mathrm{acc}.Math.}={\phi }_{\mathrm{MS}}^b-\frac{\mathrm{Qfb}}{\mathrm{CBOX}}-\frac{\mathrm{Cb}}{\mathrm{CBOX}}\times 2\times \mathrm{\phi B}+\frac{q\times \mathrm{Nb}\times \mathrm{tsi}}{2\times \mathrm{CBOX}}$ Eq. 6   Case-2: The Back-Surface of Front-Silicon film that interfaces the BOX is   inverted:   In that case the VGB in Eq. 3 is large enough to bring the Ψsb equaling 2 × φB,   and the VTHO of Eq. 1 collapses to: [00018]$\mathrm{VTHO}={\phi }_{\mathrm{MS}}^f-\frac{q\times \mathrm{Qff}}{\mathrm{CFox}}+2.Math.\mathrm{\phi B}+\frac{q\times \mathrm{NB}\times \mathrm{tsi}}{2\times \mathrm{CFox}}$ Eq. 7   Case-3: The Back-Surface of Front-Silicon film that interfaces the BOX is   accumulated:   At the onset of accumulation the Ψsb of Eq. 1 equals 0, and the VTHO of Eq. 1   converges to: [00019]$\mathrm{VTHO}={\varphi }_{\mathrm{MS}}^f-\frac{q\times \mathrm{Qff}}{\mathrm{CFox}}+2.Math.\mathrm{\varphi \varphi }-\frac{q\times \mathrm{NB}\times \mathrm{tsi}}{2\times \mathrm{CFox}}+\frac{\mathrm{.Math.o}\times \mathrm{.Math.si}}{\mathrm{tsi}\times \mathrm{CFox}}\times 2\times \mathrm{\varphi B}$ Eq. 8  // Accounting to Short-Channel-Effects (SCE).   There exists a RollOff component and a RollUp component to the threshold- voltage. Both become significant at the lower LGeff value.They also become significant at the higher bias to Drain. VD VT = VTHO + RollOff(LGeff, VD) + RollUp(LGeff, VD) Eq. 9  // RollOff is due to combined effect from DIBL due toVD and short LGeff, and from the aggregate transversal barrier lowering (between Front-Gate & Back-Gate); Eq. 10 below gives good proxy to a relatively small lowering of the transversal barrier at 2 × φB when - [00020]$\mathrm{Roll}.Math.\mathrm{Off}\left(\mathrm{LGeff},\mathrm{VD}\right)=-\left[\left(2\times \mathrm{\phi B}-\mathrm{\psi o}\right)+\mathrm{VD}\times e^{\frac{-\mathrm{LGeff}}{{\gamma }^4\times \mathrm{lc}}}\right]$ Eq. 10 [00021]${\psi }_0=\mathrm{vth}\times \ln \left(\frac{N^{-}\times \mathrm{NA}}{{\mathrm{ni}}^2}\right)$ [00022]$\mathrm{lc}=\sqrt{\frac{\mathrm{.Math.o}\times \mathrm{.Math.si}\times \mathrm{tox}\times \mathrm{tsi}}{\mathrm{.Math.o}\times \mathrm{.Math.ox}}}$  // RollUp is due to HALO encroachment under the Gate. It becomes significant in short- channels (short LGeff) as it then constitutes significant portion of higher doping in Body. It also becomes more pronounced with lower VD as DIBL becomes then suppressed; It is modeled function of the difference between Threshold-Voltage in HALO and in Body relative to an applied VD and the LGeff. [00023]$\mathrm{RollUp}\left(\mathrm{LGeff},\mathrm{VD}\right)=2\times \left[K-\frac{1}{\partial \mathrm{HALO}}\right].Math. \times {\Psi }_{\mathrm{imp}}\times \partial \mathrm{HALO}\times e^{\frac{-\mathrm{LGeff}}{2\times {\left(\gamma \right)}^4\times \mathrm{lc}}}$ Eq. 11 [00024]$K=\frac{2}{\mathrm{lc}}\times \left[\sqrt{\frac{\mathrm{VTHOP}-\mathrm{VTHO}}{\mathrm{VD}}}\right]$ [00025]$\mathrm{VTHOP}.Math.\stackrel{\sim }{=}.Math.{\phi }_{\mathrm{MS},\mathrm{Pocket}}^f-\frac{q\times \mathrm{Qff}}{\mathrm{Cof}}+2.Math.\mathrm{\phi p}+\frac{q\times \mathrm{NA}\times \mathrm{xd}}{\mathrm{CFox}}$ [00026]$\mathrm{xd}=2\times \sqrt{\frac{\mathrm{.Math.o}\times \mathrm{.Math.si}\times \mathrm{\phi p}}{q\times \mathrm{NA}}}$ [00027]$\mathrm{\phi p}=\mathrm{vth}\times \ln \left(\frac{\mathrm{NA}}{\mathrm{ni}}\right)$ ψ.sub.imp = ψo − φB ∂HALO = Wp + with ofP_Halo // Sec. IV - Extracting the WGeff that meets the targeted saturated drive current at the targeted Front-Gate bias and VT. (Source: KWYRO LEE, MICHAEL SHUR, TOR A. FJELDLY, and TROND YTTERDAL, Semiconductor Device Modeling for VLSI, New Jersey: Prentice Hall, pp. 238-256, 1993).   Case-1: Drive current depends on Saturation-velocity due to the Short-Channel   effect defined when   [00028]$\frac{\mathrm{vsat}}{\mathrm{\mu e}}\times \mathrm{LGeff}.Math.<<\mathrm{VGS}.Math.-\mathrm{VT}$ Eq. 12   Then the WGeff is:   [00029]$\mathrm{WGef}.Math.f=\frac{\mathrm{ISat}}{\mathrm{vsat}\times \mathrm{CFox}\times {\left(\mathrm{VGS}-\mathrm{VT}\right)}^{-}}$ Eq. 13   [00030]$\mathrm{VKnee}=\frac{\mathrm{vsat}}{\mathrm{\mu e}}\times \mathrm{LGeff}$ Eq. 14   The Isat in Eq. 13 is the targeted Saturation drive current, and The VKnee of   Eq. 14 is the device Knee-voltage between linear and saturated drive current.   Case-2: Drive current depends on low-field Mobility due to relatively long   LGeff. This occurs when the criteria of Eq. 12 is not met.   [00031]$\mathrm{WGeff}=\frac{2\times \mathrm{ISat}\times \mathrm{LGeff}}{\mathrm{\mu e}\times \mathrm{CFox}\times {\left(\mathrm{VGS}-\mathrm{VT}\right)}^2}$ Eq. 15   VKnee = VGS − VT Eq. 16 Given that the ISat and the VT targets are defined and so is the VGS, and rest of process parameters are known, the WGeff is extracted either from Eq. 13 or from Eq. 15 depending on the magnitude of the LGeff relative to Eq. 12. (The model parameters for ISAT are extracted from built-in Test-structures). // Sec. V - Determining the Vdrop per SPAC/2 segment. (Source: STREETMAN, Solid State Electronic Devices. 4th ed. New Jersey: Prentice Hall, pp. 244-247, 1995). [00032]${\mathrm{IBJT}}_{\mathrm{Drain}}\left(\mathrm{Vdrop}\right)=q\times \left(\frac{\mathrm{SPAC}\times \mathrm{tsi}}{2\times \mathrm{const}}\right)\times \frac{\mathrm{Dn}}{\mathrm{Ln}}\times \left(K.Math..Math.1.Math.\left(\mathrm{Vdrop}\right)\times e^{-\partial \mathrm{HALO}/\mathrm{Ln}}-K.Math..Math.2.Math.\left(\mathrm{Vdrop}\right)\times e^{\partial \mathrm{HALO}/\mathrm{Ln}}\right)$ Eq. 17 [00033]${\mathrm{IBJT}}_{\mathrm{Source}}\left(\mathrm{Vdrop}\right)=q\times \left(\frac{\mathrm{SPAC}\times \mathrm{tsi}}{2\times \mathrm{const}}\right)\times \frac{\mathrm{Dn}}{\mathrm{Ln}}\times \left[\frac{\frac{{\mathrm{ni}}^2}{\mathrm{Np}}\times \left(e^{\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}+e^{-\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}\right)+2\times \frac{{\mathrm{ni}}^2}{\mathrm{NP}}}{e^{\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}-e^{-\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}}\right]$ Eq. 18 The const in Eq. 17 & Eq. 18 accounts to an effective-area because the Vdrop varies throughout the P_Pocket alongside the Gate-width. [00034]$K.Math..Math.1.Math.\left(\mathrm{Vdrop}\right)=\frac{\frac{{\mathrm{ni}}^2}{\mathrm{Np}}\times e^{\frac{\mathrm{Vdrop}}{n\times \mathrm{vth}}}\times e^{\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}+\frac{{\mathrm{ni}}^2}{\mathrm{Np}}}{e^{\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}-e^{-\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}}$ [00035]$K.Math..Math.2.Math.\left(\mathrm{Vdrop}\right)=\frac{-\frac{{\mathrm{ni}}^2}{\mathrm{Np}}-\frac{{\mathrm{ni}}^2}{\mathrm{Np}}\times e^{\frac{q\times \mathrm{Vdrop}}{n\times \mathrm{vth}}}\times e^{-\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}}{e^{\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}-e^{-\frac{\partial \mathrm{HALO}}{\mathrm{Ln}}}}$ Magnitude for Bipolar current is set order(s) of magnitude lower than the ISat, and the corresponding Vdrop is extracted. (The model parameters for the Bipolar current are extracted from built-in Test-structures). // Sec. VI - Determining the corresponding Body-Current (Ib) for the targeted ISat and VDS. That is II-current. (Source: X. GU et al., “A Surface-Potential-Based Extrinsic Compact MOSFET Model”, Tech. Proceed. 2003 Nanotech. Conf. and Trade Show, vol. 2, pp. 364-367, San Francisco., February 2003). [00036]$\mathrm{Ib}=\mathrm{ISat}\times \left[\frac{\alpha }{\Omega }\times \left(\mathrm{VDS}-\Gamma \times \mathrm{VKnee}\right)\times e^{-\frac{\mathrm{lm}\times \Omega }{\mathrm{VDS}-\Gamma \times \mathrm{VKnee}}}\right]$ Eq. 19 Ib is extracted from Eq. 19. (The model parameters for Ib are extracted from built-in Test-structures).