Apparatus for treating neurological disorders by electrostimulation and method for processing neural signals collected by the said apparatus

Abstract

The present disclosure relates to apparatuses and methods for treating neurological disorders by electro-stimulation. In some embodiments, the apparatus includes a stimulation module configured to generate a stimulation signal to be sent to at least one implantable electrode, and an acquisition module configured to acquire a signal measured by the at least one implantable electrode from a patient. The acquisition module may include a front-end block configured to amplify a potential difference of input signals (V1a, V2a) received by the acquisition module and to filter a stimulus artifact by cutting off frequencies above a predefined frequency band. The front-end block may include a multi-stage fully-differential switched capacitor circuit configured for discrete-time signal processing.

Claims

1. An apparatus comprising: a stimulation module configured to generate a stimulation signal to be sent to at least one implantable electrode, and an acquisition module configured to acquire a signal measured by the at least one implantable electrode from a patient, wherein the acquisition module comprises a front-end block configured to amplify a potential difference of input signals (V.sub.1a, V.sub.2a) received by the acquisition module and to filter a stimulus artifact by cutting off frequencies above a predefined frequency band; characterized in that the front-end block comprises a multi-stage fully-differential switched capacitor circuit configured for discrete-time signal processing.

2. The apparatus of claim 1, wherein the front-end block comprises a pre-filter stage and a suppression filter stage positioned downstream from the pre-filter stage.

3. The apparatus of claim 2, wherein each of the pre-filter stage and the suppression filter stage comprising a fully-differential switched capacitor circuit configured for discrete-time signal processing.

4. The apparatus of claim 3, wherein the pre-filter stage comprises a first fully-differential low-pass switched capacitor filter, clocked at a first clock frequency.

5. The apparatus of claim 4, wherein the suppression filter stage comprises a second fully-differential low-pass switched capacitor filter, clocked at a second clock frequency.

6. The apparatus of claim 4, wherein the fully-differential switched capacitor filter of the pre-filter stage and of the suppression filter stage comprises at least one bilinear switched capacitor integrator.

7. The apparatus of claim 6, wherein the at least one bilinear switched capacitor integrator is configured to implement correlated double sampling.

8. The apparatus of claim 6, wherein the at least one bilinear switched capacitor integrator comprises two inputs (V.sub.1a,V.sub.2a) which are alternatively connectable to one end of two input capacitors (C.sub.1, C.sub.2), the other end of the two input capacitors (C.sub.1, C.sub.2) being configured to alternatively connect to a reference voltage source (V.sub.ref) or, each respectively, to one of two inputs of an operational amplifier.

9. The apparatus of claim 8, wherein each input of the operational amplifier being connectable to one respective output of the operational amplifier through interposition of a first (C.sub.3,C.sub.5) and a second (C.sub.4,C.sub.6) pair of feedback capacitors, respectively.

10. The apparatus of claim 9, wherein the feedback capacitor pairs (C.sub.3,C.sub.5) and (C.sub.4,C.sub.6,) comprise each a first (C.sub.3,C.sub.4) and a second (C.sub.5,C.sub.6) feedback capacitors connected in parallel, and are configured to alternatively connect to the respective input of the operational amplifier .

11. The apparatus of claim 6, wherein the at least one bilinear switched capacitor integrator comprises two inputs (V.sub.1a,V.sub.2a) which are alternatively connectable to one end of two input capacitors (C.sub.1, C.sub.2), the other end of the two input capacitors (C.sub.1, C.sub.2) being configured to alternatively connect to a reference voltage source (V.sub.ref) or, each respectively, to one of two inputs of an operational amplifier, each input of the operational amplifier being connectable to one respective output of the operational amplifier through interposition of a first (C.sub.3) and a second (C.sub.4) feedback capacitor, respectively.

12. The apparatus of claim 3, wherein the fully-differential switched capacitor circuit of the pre-filter stage and/or of the suppression filter stage is implemented as ladder filter comprising a plurality of switched capacitor integrators in an active emulation of lossless LC ladder structure.

13. The apparatus of claim 5, wherein the first fully-differential switched capacitor filter of the pre-filter stage has an order lower than an order of the second fully-differential switched capacitor filter of the suppression filter stage.

14. The apparatus of claim 5, wherein the first clock frequency of the first fully-differential switched capacitor filter of the pre-filter stage is greater than the second clock frequency of the second fully-differential switched capacitor filter of the suppression filter stage.

15. The apparatus of claim 4, wherein the first clock frequency is at least 1 KHz.

16. The apparatus of claim 5, wherein a first cut-off frequency of the first fully-differential switched capacitor filter of the pre-filter stage is greater than a second cut-off frequency of the second fully-differential switched capacitor filter of the suppression filter stage.

17. The apparatus of claim 5, wherein a first cut-off frequency of the first fully-differential switched capacitor filter of the pre-filter stage is at least 50 Hz and is lower than the second clock frequency.

18. The apparatus of claim 5, wherein a second cut-off frequency of the second fully-differential switched capacitor filter of the suppression filter stage is in the range of about 35-2000 Hz.

19. The apparatus of claim 1, wherein the acquisition module further comprises an A/D converter block connected downstream from the front-end block.

20. The apparatus of claim 19, wherein the A/D converter block optionally comprises a delta-sigma converter.

21. The apparatus of claim 19, wherein the A/D converter block comprises a fully-differential switched-capacitor circuit.

22. The apparatus of claim 19, wherein the A/D converter block comprises a first sampling stage, followed by a filter stage configured for removing a quantization noise and a decimation stage.

23. The apparatus of claim 1, wherein the acquisition module further comprises at least one functional module between: a first functional module configured for receiving an input synchronization signal coming from the stimulation module for disconnecting or grounding the inputs of the front-end block during stimulus pulses generated by the stimulation module, the first functional module being connected upstream from the front-end block; and/or a second functional module configured for eliminating high frequencies in a signal produced by the operation of the first functional module; and/or a third functional module configured for providing high-pass filtering so as to mitigate offset potentials at the at least one implantable electrode.

24. A method comprising: receiving a signal using at least one implantable electrode; amplifying and pre-filtering the signal acquired by using a first stage comprising a fully-differential switched capacitor circuit configured for discrete-time signal processing; and filtering the amplified and pre-filtered signal by cutting off frequencies above a predefined frequency band using a second stage comprising a fully-differential switched capacitor circuit configured for discrete-time signal processing.

25. The method of claim 24, wherein amplifying the signal or filtering the amplified signal comprises correlated double sampling.

26. The method of claim 24, wherein amplifying the signal is performed using a first fully-differential switched capacitor filter, clocked at a first clock frequency.

27. The method of claim 26, wherein the step of filtering the amplified signal is performed using a second fully-differential switched capacitor filter, clocked at a second clock frequency.

28. The method of claim 27, wherein the first clock frequency is greater than the second clock frequency.

29. The method of claim 27, wherein a first clock signal at the first clock frequency and/or a second clock signal at the second clock frequency are configured to time an alternative connection and disconnection of second feedback capacitors (C.sub.5,C.sub.6) of feedback capacitor pairs (C.sub.3,C.sub.5) and (C.sub.4,C.sub.6) to the input of an operational amplifier.

30. The method of claim 27, wherein the first fully-differential switched capacitor filter is a low-pass filter with a first cut-off frequency and the second fully-differential switched capacitor filter is a low-pass filter with a second cut-off frequency smaller than the first cut-off frequency.

31. The method of claim 27, wherein the first fully-differential switched capacitor filter of the pre-filter stage has an order lower than an order of the second fully-differential switched capacitor filter of the suppression filter stage.

32. The method of claim 25, wherein the correlated double sampling is implemented using a bilinear switched capacitor integrator, and wherein the bilinear switched capacitor integrator comprises two inputs (V.sub.1a,V.sub.2a) which are alternatively connectable to one end of two input capacitors (C.sub.1, C.sub.2), another end of the two input capacitors (C.sub.1, C.sub.2) being configured to alternatively connect to a reference voltage source (V.sub.ref) or, each respectively, to one of two inputs of an operational amplifier.

33. The method of claim 32, wherein each input of the operational amplifier being connectable to one respective output of the operational amplifier through interposition of a first pair (C.sub.3,C.sub.5) and a second pair (C.sub.4,C.sub.6) of feedback capacitors, respectively.

34. The method of claim 33, wherein the first pair (C.sub.3,C.sub.5) and the second pair (C.sub.4,C.sub.6) of feedback capacitors comprise each a first (C.sub.3,C.sub.4) and a second (C.sub.5,C.sub.6) feedback capacitors connected in parallel, and are configured to alternatively connect to the respective input of the operational amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) With reference to the attached drawings, further features and advantages of the present invention will be shown using the following detailed description of some of its preferred embodiments.

(2) According to the above description, the several features of each embodiment can be unrestrictedly and independently combined with each other in order to achieve the advantages specifically deriving from a certain combination of the same.

(3) FIG. 1 shows a schematic view of a preferred embodiment of a brain stimulation apparatus for treating the neurological disorders;

(4) FIGS. 2a and 2b show two block diagrams of an acquisition module adopted by the apparatus of FIG. 1;

(5) FIGS. 2c and 2d respectively shows a block diagram of the front-end block and of the A/D converter block of the acquisition module adopted by the apparatus of FIG. 1;

(6) FIG. 3 is a schematic view of a first preferred embodiment of an integrator forming a basic building unit used for implementing the filter stages of the front-end block of the acquisition module of FIG. 2a and FIG. 2b;

(7) FIG. 4 is a schematic view of a conventional fully-differential switched capacitor integrator;

(8) FIG. 5 is a plot that depicts the CMRR between the conventional switched capacitor integrator according to FIG. 4 and the improved bilinear fully-differential switched capacitor integrator according to FIG. 3 in the presence of a capacitive mismatch of 10% between input capacitances;

(9) FIG. 6 is a schematic view of a second preferred embodiment of an integrator forming a basic building unit used for implementing the filter stages of the front-end block of the acquisition module of FIG. 2a and FIG. 2b, and FIG. 6a depicts a timing diagram of clock signals that control the operation of the integrator of FIG. 6;

(10) FIG. 7 is a schematic view of a pre-filter stage of the front-end block of the acquisition module of FIGS. 2a and 2b;

(11) FIGS. 8a-d are graphs illustrating the frequency components of a signal at various stages within the front-end block of the acquisition module of FIG. 2a and FIG. 2b;

(12) FIGS. 9a and 9b are two logarithmic plots showing the signal power during stimulation and in absence of stimulation, processed using the prior art single-ended analog front end and a fully-differential switched capacitor front end, respectively.

DETAILED DESCRIPTION

(13) In the figures and in the following description, identical reference numerals or symbols are used to indicate constructive elements with the same function. Moreover, for the sake of clarity of illustration, it is possible that some reference numerals are not repeated in all of the figures. While examples and variations of the invention are depicted and described herein, it should be understood that there is no intention to limit the invention to the specific examples and variations embodiments described below, but on the contrary, the invention is meant to cover all the modifications or alternative and equivalent implementations which fall within the scope of protection of the invention as defined in the claims.

(14) Expressions like “example given”, “etc.”, “or” indicate non-exclusive alternatives without limitation, unless expressly differently indicated. Expressions like “comprising” and “including” have the meaning of “comprising or including, but not limited to” unless expressly differently indicated. Further, a “module” or a “functional module” as referenced throughout may refer to an assembly of electrical circuitry and/or electrical components that are arranged and connected to perform one or more functions as described herein, and/or may refer to a special purpose computer that is programmed to perform the functions described herein.

(15) With reference to FIG. 1, one variation of an apparatus for treating neurological disorders is shown, wholly indicated with 10.

(16) In particular, the apparatus illustrated in FIG. 1 is suitable for the adaptive deep brain stimulation being configured to detect biopotentials (e.g., local field potentials or LFPs) from a stimulating electrode or from contiguous electrodes, for correlating such signals to the stimulation effects and/or for adapting stimulation parameters in order to facilitate patient therapy.

(17) The apparatus for treating neurological disorders 10 comprises at least one probe or electro-catheter 11 configured to be implanted in the brain of a patient to administer electrical stimulation. The probe or electro-catheter 11 may comprise at least three metallic contacts or leads accessible through external connections, also called electrodes 12. However, in other variations, the electrodes may not be located on the same electro-catheter (e.g., an apparatus for adaptive DBS may comprise two or more electro-catheters and the electrodes may be located on two different electro-catheters).

(18) The apparatus for treating neurological disorders 10 may comprise one or more implantable probes where each probe may comprise one or more electrodes. The apparatus 10 may also comprise a connector or probe extension for each of the implantable probes. A probe (e.g., probe 11) may have a distal portion and a proximal portion. The one or more electrodes (for delivering electrical stimulation and/or neural activity data acquisition) are located on the distal portion and one or more connector contacts are located on the proximal portion, and one or more wires within the probe electrically connect the electrodes with the connector contacts. A probe 11 may comprise any number of electrodes 12, for example, 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 24, 36, 48, 64, 96, etc. and a corresponding number of connector contacts. A probe extension may have a distal portion having a connector block with a receptacle housing enclosing one or more conductive contacts, a proximal portion having stimulation device (e.g., apparatus 10) connector contacts, where each of the stimulation device connector contacts corresponds with a conductive contact in the receptacle housing via one or more wires, and an elongated body between the proximal portion and the distal portion. A probe extension may comprise any number of conductive contacts, for example, 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 24, 36, 48, 64, 96, etc. and a corresponding number of stimulation device connector contacts. The number of conductive contacts of the probe extension may be the same as, or greater than, the number of electrodes on the probe to which the probe extension is connected. The distal portion of the probe may be implantable into the target brain region, while the proximal portion of the probe may extend outside of the brain tissue and connect with a distal portion of a probe extension. The receptacle housing of the probe extension may be configured to retain the proximal portion of the probe such that the connector contacts of the probe electrically connect with the conductive contacts of the probe extension such that the electrodes at the distal portion of the probe are electrically coupled to the stimulation device connector contacts at the proximal portion of the probe extension. The stimulation device connector contacts may be configured to be coupled to a port or connector of a processing and stimulation device 14 (e.g., a header interface). In some variations, the receptacle housing may comprise an attachment mechanism to engage or retain the proximal portion of the probe within the receptacle housing. Optionally, the probe extension may comprise a connector sleeve or boot comprising an electrically insulating material that is disposed over at least a portion of the receptacle housing to help electrically isolate the connector contacts of the probe and the conductive contacts of the probe extension from surrounding tissue. The elongated body of the probe extension may have a constant diameter between the distal portion and the proximal portion, or may have a varying diameter along its length. For example, the diameter of a segment of the elongated body may be larger (e.g., thicker) where that segment is intended to be located at the interface between brain tissue and the skull or skin. This may help reduce excessive twisting, torqueing, and/or bending of the wires within the elongated body of the probe extension, thereby reducing the mechanical wear on the wires and/or helping to prolong the usable life of the probe extension.

(19) While the apparatus for treating neurological disorders 10 depicted in FIG. 1 comprises a probe 11 having four metallic contacts or electrodes 12, other variations of probes may comprise any number of electrodes (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 16, 18, 20, 25, 30, 36, 48, or more). As described previously, an apparatus for treating neurological disorders 10 may comprise any number of probes (e.g., two or more), where each probe may have any number of electrodes. For example, an apparatus for treating neurological disorders 10 may comprise a first probe with a first electrode and a second probe with a second electrode. In use, the first probe may be implanted in a first brain region and the second probe may be implanted in a second brain region (e.g., for bilateral stimulation). In another variation, an apparatus for treating neurological disorders 10 may comprise two probes, where each probe may have four electrodes (for a total of eight channels) or may have eight electrodes (for a total of sixteen channels).

(20) In one variation, a probe 11 may comprise multiple electrodes where a first electrode is a stimulating electrode that delivers electrical stimulation and a second electrode is a measurement electrode that acquires neural activity signals. For example, a first plurality of electrodes (which may or may not be adjacent to each other) may be used for stimulating and a second plurality of electrodes (which may or may not be adjacent to each other, or may be arranged in alternating fashion with the first plurality of electrodes) may be used for acquiring neural activity signals. Alternatively or additionally, the same electrode(s) may be used for both neural activity signal acquisition and electrical stimulation simultaneously or sequentially. DBS probes may comprise one or more cylindrical or disc-shaped electrodes having a height from about 0.5 mm to about 3 mm, e.g., about 1.5 mm, and a diameter from about 0.5 mm to about 2 mm, e.g., about 1.27 mm. In some variations, DBS probes may comprise two or more cylindrical electrodes (for example, 2, 4, 6, 10, 12, 15, 16, 20, etc. or more electrodes). Alternatively or additionally, DBS probes may comprise planar electrodes and/or sharp electrodes having a geometry selected at least in part based on the target neural structure or brain region. The spacing between two electrodes may be from about 0.25 mm to about 2 mm, e.g., about 0.5 mm, and optionally, an insulator may be disposed between two electrodes and/or around an electrode to reduce electrical coupling or cross-talk between electrodes. An insulator may comprise, for example, polyurethane and/or polyimide and/or the like. The electrodes may be made of any metal or any metallic alloy, for example, a platinum-iridium alloy.

(21) In the embodiment illustrated in FIG. 1, the electrodes 12 are connected to a processing and stimulation device 14 that comprises three functional modules connected together in a feedback and interoperating configuration: a stimulation module 16, a data acquisition module 20 and a control module 18.

(22) In one variation, the stimulation device 14 may comprise sixteen channels, which may be connected to two probes each having eight electrodes, or four probes each having four electrodes, or eight probes each having two electrodes, etc. There may be fewer electrodes than channels, for example, although the stimulation device 14 may be configured to accommodate sixteen channels (e.g., for sixteen stimulation and/or LFP acquisition electrodes), a particular instance of an apparatus for treating neurological disorders 10 or DBS system may comprise eight electrodes (e.g., two probes each having four electrodes) or four electrodes (e.g., a single probe having four electrodes).

(23) The stimulation module 16 is adopted to generate a stimulation signal and to send it to the electrodes 12. The stimulation module 16 may comprise pulse or function generator comprising a voltage source and/or current source and circuitry configured to produce electrical pulses with certain parameter values determined by a user and/or controller, and may also comprise wires that transmit the electrical pulses to the probe, which deliver the electrical pulses to the brain region.

(24) In some variations, the stimulation module may comprise a waveform generator (e.g., a pulse or function generator), a current controller, and a multiplexer, one or more of which may be configured to receive command signals from the control module or main processor 18. The command signals may comprise electrical stimulation parameter data, including, but not limited to, stimulation amplitude, pulse width, pulse frequency, duty cycle, and/or the specific probe(s) and/or electrode(s) from which electrical stimulation with the specified parameters is to be delivered. The current controller may be configured to set an electrical stimulation amplitude specified by the command signals, and/or the waveform generator may be configured to generate current or voltage pulses having the pulse width and/or pulse frequency specified by the command signals. The multiplexer may be configured to electrically connect the probes and/or electrodes specified by the command signals with the current controller and/or waveform generator. In some variations, the multiplexer may comprise a multiplexer array that may be configured according to command signals from the main processor so that the electrical pulses from the waveform generator may be channelled to the selected probes and/or electrodes. The connectivity between the waveform generator and the electrodes may be arranged by the multiplexer in a monopolar stimulation configuration and/or a bipolar stimulation configuration. In a monopolar configuration, one or more electrodes may be connected to one or more active (e.g., positive) terminals of the waveform generator (with a return pad placed elsewhere on a patient). In a bipolar configuration, a first set of one or more electrodes may be connected to one or more active (e.g., positive) terminals of the waveform generator while a second set of one or more electrodes (e.g. distinct from the first set of electrodes) may be connected to one or more return (e.g., negative) terminals of the waveform generator.

(25) In some variations, the stimulation module 16 may be configured to generate a stimulation signal V.sub.stim that may be characterised by a set of parameters, and to transmit the stimulation signal V.sub.stim to one or more of the electrodes 12. For example, the stimulation module 16 may comprise a pulse generator having a current source (and/or voltage source) that generates electrical signals that have parameters specified by a user and/or the control module. In some variations, a pulse generator may form output pulses having specified amplitude, frequency and/or pulse width or duration values. Optionally, a pulse generator may generate a pulse sequence having two pulses or more pulses repeated with a duty cycle specified by a user and/or the control module 18, and the control module 18 may adjust the pulse duty cycle in accordance with one or more properties of the acquired neural activity signals (e.g., any of the patterns or properties described herein).

(26) The data acquisition module 20 is responsible for the acquisition of a signal representative of the cerebral activity coming from the brain of the patient, e.g. LFP signals that may represent the cerebral activity in the brain region where the probe 11 is implanted. The acquisition module 20 is in electrical communication with the probe 11 which may be, in some variations, the same probe used to electrically stimulate the brain region. The acquisition module 20 and/or the probe 11 may be configured to acquire neural activity signals, such as local-field potentials (LFPs), resulting from the activity of the brain region in proximity to the probes 11. The acquisition module 20 may comprise an acquisition processor and memory that stores and analyzes the acquired neural activity signals.

(27) The control module 18 implements an adaptive control of the stimulation module 16 based on the signal acquired by the acquisition module 20. The control module may have circuitry configured to facilitate communication between the acquisition module 20 and the stimulation module 16, coordinate signalling between the acquisition module 20 and the stimulation module 16, and/or to perform additional computations on the acquired neural activity signals.

(28) The control module 18 may be part of either the acquisition module or the stimulation module, or may be a separate module. In some variations, the control module comprises circuitry configured to regulate/coordinate the operation of the stimulation module based on signals from the acquisition module (e.g., based on LFP signals indicative of neural activity). The control module may have a control module (main) processor and memory that analyzes and stores the acquired neural activity signals and/or signals from the acquisition module. In some variations, the control module may comprise circuitry that regulates the power supplied to the stimulation module, for example, in coordination with the electrical stimulation parameters determined by the acquisition module and/or the acquired neural activity signals. The properties or parameters of the electrical stimulation may be determined by the acquisition module and/or the control module. For example, the processors of the acquisition module and/or the control module may analyze the acquired and/or stored neural activity signals to identify variations or changes in the patterns or characteristics of neural activity signals. The control module may provide command signals to the pulse generator of the stimulation module to change the parameters of the electrical stimulation according to the changes in the neural activity signals detected or extracted by the acquisition module. The control module may also comprise a battery (e.g., a rechargeable battery), and circuitry configured to charge and/or measure the charge remaining on the battery. For example, the control module may comprise a rechargeable battery, an inductive link for charging the battery and an inductive coil for facilitating the energy transfer between an external charging device and the stimulation device (which may be implanted in the patient). Optionally, the control module may comprise wireless transmission interface (e.g., a transceiver) including an RF chip and an RF antenna for signal transmission between the implantable stimulation device and an external device. In some variations, the acquisition module may comprise a processor that is configured to calculate the spectral power values of acquired neural activity signals, and the calculated power values may be transmitted to the control module, and the control module processor may be configured to derive stimulation parameters according to the power values and general command signals to the pulse generator to adapt or adjust the parameters of the electrical stimulation. Optionally, the control module may comprise additional sub-modules with circuitry configured for power supply management, electrode impedance checking, and/or calibration and/or diagnostic analyses (e.g., troubleshooting) of the stimulation module.

(29) Going back to the acquisition module 20 of FIG. 1, its main function is to measure the electric field variations of the local biopotentials directly sensing the difference between the electric potentials V.sub.1 and V.sub.2 referred to a common electrode 17 and to amplify such difference so as to reach a voltage level useful for the analog-to-digital conversion necessary for the signal processing.

(30) Accordingly, the acquisition module 20 may comprise input ports V.sub.1 and V.sub.2 that are each connected to different electrodes 12 on the probe 11 and electrical circuits that are configured to measure the electric field variations of the local biopotentials or local field potentials (LFPs) based on the signals from the input ports V.sub.1 and V.sub.2. Electrical circuits of the acquisition module may comprise one or more processing units or processors (e.g., a CPU, and/or one or more field-programmable gate arrays, and/or one or more application-specific integrated circuits) that may be configured to perform computational operations, one or more memory elements, one or more amplifiers, one or more filters, and/or one or more analog-to-digital converters.

(31) As depicted in FIG. 2b, the acquisition module 20 may measure electric field variations by sensing changes in the electric potentials V.sub.1 and V.sub.2 (e.g., difference(s) between V.sub.1 and V.sub.2, or values of V.sub.1 or V.sub.2 as referenced to a common or ground electrode 17) using a pre-amplifier and may amplify the changes (and/or any electric field variations) using an amplifier. The amplified output may be converted to a digital signal using an analog-to-digital converter, and the digital signal may be transmitted to the control module 18 (shown in FIG. 1) for further analysis and processing.

(32) In some variations, the acquisition module 20 may comprise an acquisition processor that is configured to transform the acquired neural activity signals (e.g., LFPs) into spectral signals (e.g., spectral power values) that represent cerebral activity in the frequency domain (i.e., frequency-domain representation). For example, an acquisition processor of the acquisition module may be configured to carry out a Fourier Transform (e.g., a Fast-Fourier Transform or a Discrete-Fourier Transform) of the neural activity signals from input ports V.sub.1 and V.sub.2. The acquisition processor may comprise a general-purpose microprocessor that executes instructions from a software program to perform the frequency-domain signal transformation. Alternatively or additionally, the acquisition processor may comprise a digital signal processor (DSP) that has specialized electrical circuitry for performing the frequency-domain signal transformation. Alternatively or additionally, the acquisition processor may comprise an FPGA and/or ASIC configured for performing the frequency-domain signal transformation. Additionally, the acquisition processor(s) of the acquisition module 20 may be configured to calculate the power values of the neural activity signals in certain frequency bands of interest (e.g., the low-frequency band, alpha frequency band, beta frequency band, gamma frequency band, and/or any range of frequencies as may be desirable). In some variations, the acquisition processor may perform the power calculation in the time domain. The acquisition processor may comprise a band pass filter followed by a rectifier to perform the power calculation in the time domain. In some variations, the processor(s) of the acquisition module 20 may comprise an integral block and a derivative block (not illustrated) of the power values in order to highlight respectively slow and fast time changes of the power values. An integral or integration block may be configured to combine power values over time (e.g., by calculating an average value, which may be a moving average value) to help enhance slower changes or longer-term trends in power values. A derivative block may be configured to combine power values to help enhance faster or instantaneous changes in power values.

(33) As shown in FIG. 2b more in detail, the acquisition module 20 comprises a front-end block 27 (shown in FIG. 2c) and an A/D converter block 23. In the depicted preferred embodiment, the A/D converter block 23 may comprise a delta-sigma converter.

(34) The front-end block 27 may comprise a pre-filter stage 21 and a suppression filter stage 22. The pre-filter stage 21, the suppression filter stage 22 and the A/D converter block 23 may comprise one or more fully-differential switched-capacitor circuits. In detail, the pre-filter stage 21 may comprise a fully-differential switched-capacitor architecture which may be configured for both amplification and antialiasing filtering.

(35) The suppression filter stage 22 may comprise a fully-differential switched-capacitor architecture which provides for low-pass filtering and additional amplification.

(36) The A/D converter block 23 may comprise a switched-capacitor network which provides for amplification and analog-to-digital signal conversion.

(37) The pre-filter stage 21 may be configured to differentially amplify the signal to a value greater than the input referred noise of the suppression filter stage 22 without compromising the minimum detectable signal (in the order of μV) and by avoiding the saturation of the recording chain. Accordingly, as schematically depicted in FIG. 3, the pre-filter stage 21 may comprise a fully-differential operational amplifier 21a, a plurality of input capacitors C.sub.1,C.sub.2 connected at its input terminals and feedback capacitors C.sub.3,C.sub.4 connected between its input and output terminals. The gain of the pre-filter stage 21 is configured by choosing the values of the input and the feedback capacitors. Variations of pre-filter stage circuitry are further described below.

(38) The pre-filter stage 21 and/or suppression filter stage 22 may comprise a ladder configuration of the fully-differential low-pass switched capacitor filters. The ladder configuration makes use of basic building units, such as those depicted in FIG. 3. In this variation, the basic building unit is a first-order bilinear switched capacitor integrator which allows an improvement of the CMRR at the frequencies of interest as compared to the CMRR of conventional integrators (FIG. 4). As shown in FIG. 5, the basic building unit of FIG. 3 achieves higher CMMR compared to the conventional integrator of FIG. 4.

(39) The input network 21b of the used integrator (FIG. 3) adopts a parasitic insensitive switched capacitor configuration being each node of the switched capacitor connected between two voltage sources V.sub.1a, V.sub.2a, or between a common reference voltage V.sub.ref and virtual ground.

(40) In this way a differential sampling can be performed by subtracting the negative from the positive signal at the front-end of the acquisition chain during each sampling period.

(41) In detail, the inputs V.sub.1a and V.sub.2a are alternatively connected to one end of two input capacitors C.sub.1 and C.sub.2. The other end of the two input capacitors C.sub.1,C.sub.2 is alternatively connected to a reference voltage V.sub.ref or, each respectively, to one of two inputs of the fully-differential operational amplifier 21a. Each input of the operational amplifier 21a is connected to one respective differential output through interposition of a first C.sub.3 and a second C.sub.4 feedback capacitor, respectively; in this configuration, by setting the common mode of the inputs V.sub.1a and V.sub.2a equal to V.sub.ref, the inputs V.sup.+ and V.sup.− of the amplifier 21a are also polarized at this value for the whole sampling period.

(42) A common mode feedback internal to the operational amplifier ensures that in any instant V.sub.1b=−V.sub.2b.

(43) Assuming that the input voltages do not change for an overall sampling period T, the operating conditions of the circuit of FIG. 3 can be summarized by the following set of equations:

(44) $V_{1b}=\left(-V_{1a}{z}^{-1}{C}_1+V_{2a}{C}_1\right)\times \frac{1}{C_3}{V}_{2b}=\left(-V_{2a}{z}^{-1}{C}_2+V_{1a}{C}_2\right)\times \frac{1}{C_4}$
where z is the discrete-time variable used in signal-processing mathematics.

(45) The circuit schematic shown in FIG. 3 has been generalized by making all the capacitors different. This extension is made to observe that mismatches do not affect the CMRR capabilities of the circuit. In real terms, a proper design would make C.sub.1=C.sub.2 and C.sub.3=C.sub.4.

(46) The output signal V.sub.O is given by:
V.sub.O=V.sub.1b−V.sub.2b
assuming that the input signal changes at a much lower frequency than the sampling rate, thus with z.sup.−1≅1.

(47) Accordingly:

(48) $V_O=-\left(\frac{C_1}{C_3}+\frac{C_2}{C_4}\right)\left(V_{1a}-V_{2a}\right)$

(49) The advantage of this circuit can be simply seen from the last equation. If a common mode voltage ΔV.sub.C is added to both the input voltages as follows
V.sub.1a′=V.sub.1a+ΔV.sub.C
and
V.sub.2a′=V.sub.2a+ΔV.sub.C,
ideally the common mode signal ΔV.sub.C is cancelled in the output voltage V.sub.O.

(50) This property comes from the discrete-time approach of switched capacitor circuits.

(51) In a real situation, in presence of an input capacitive mismatch ΔC.sub.12, the common mode input voltage ΔV.sub.C is not totally rejected, but the bilinear switched capacitor integrator achieves a smaller differential output voltage (caused by ΔV.sub.C) compared to the traditional switched integrator of FIG. 4 with the same differential transfer gain. There is therefore an improvement in the common mode rejection, as shown in FIG. 5 with a 10% of mismatch on input capacitance.

(52) However, this CMRR figure does not remain constant but decreases as the frequency increases because the condition z.sup.−1≅1 does not hold anymore.

(53) In the second preferred embodiment depicted in FIG. 6, the basic building unit is a first-order bilinear switched capacitor integrator configured to implement correlated double sampling (CDS). This allows to achieve, in addition to optimal CMRR at the frequencies of interest, also optimal rejection of DC offset and rejection of 1/f noise compared to the conventional integrator shown in FIG. 4.

(54) Differently from the basic building unit of FIG. 3, in the basic building unit of FIG. 6 each input of the operational amplifier 21a is connected to one respective differential output through interposition of a first pair of feedback capacitors C.sub.3 and C.sub.5 and a second pair of feedback capacitors C.sub.4 and C.sub.6, respectively. More in detail, a third C.sub.5 and a fourth C.sub.6 feedback capacitor are connected in parallel to the first C.sub.3 and second C.sub.4 feedback capacitor, respectively. The feedback capacitor pairs C.sub.3,C.sub.5 and C.sub.4,C.sub.6, are alternatively connected or disconnected to the respective input of the amplifier 21a.

(55) The timing of the connections between the inputs V.sub.1a, V.sub.2a, and the input capacitors C.sub.1,C.sub.2, the input capacitors C.sub.1,C.sub.2, and the inputs of the amplifier V.sub.1a′, V.sub.2a′, the pairs of feedback capacitors C.sub.3,C.sub.5 and C.sub.4,C.sub.6 and the inputs of the amplifier V.sub.1a′, V.sub.2a′, is controlled by a plurality of clock signals as shown in FIG. 6a (i.e., four clock signals Clk1, Clk2, Clk3, Clk4). The switch connectivity state (i.e., circuit nodes that are connected by the switch) during the high state of a particular clock signal is indicated by φ.sub.1, φ.sub.2, φ.sub.1a, φ.sub.2a.

(56) Each clock signal of the plurality of clock signals Clk1, Clk2, Clk3, Clk4 has a phase shift with respect to the others. Clock signals Clk1, Clk2 control the connection between the inputs V.sub.1a, V.sub.2a and the input capacitors C.sub.1,C.sub.2, and the connection between the pairs of feedback capacitors C.sub.3,C.sub.5 and C.sub.4,C.sub.6 and the inputs of the amplifier V.sub.1a′, V.sub.2a′ with a 180° phase-shift. For example, when Clk2 is in the high state and Clk1 is in the low state, input V.sub.1a is connected to input capacitor C.sub.1, input V.sub.2a is connected to input capacitor C.sub.2, feedback capacitors C.sub.3,C.sub.5 are connected to amplifier input V.sub.1a′, and feedback capacitors C.sub.4,C.sub.6 are connected to amplifier input V.sub.2a′. Clock signals Clk3, Clk4 control the connection between the input capacitors C.sub.1,C.sub.2, and the inputs of the amplifier V.sub.1a′, V.sub.2a′ with a 180° phase-shift. For example, when Clk4 is in the high state and Clk3 is in the low state, input capacitors C.sub.1, C.sub.2 are connected to amplifier inputs V.sub.1a′, V.sub.2a′, respectively. Moreover, the clock signals Clk3, Clk4 are phase-shifted with respect to the clock signals Clk1, Clk2. FIG. 6 indicates the connectivity for each circuit switch node, each node labelled according to the clock phases φ.sub.1, φ.sub.2, φ.sub.1a, φ.sub.2a of each corresponding clock signals Clk1, Clk2, Clk3, Clk4.

(57) As shown in FIG. 7, the pre-filter stage 21 is, preferably, implemented as a third order fully-differential switched capacitor low-pass filter, e.g. using the building units of FIG. 6. More preferably, the pre-filter stage 21 is implemented as third order Cauer (e.g., elliptic) filter with a sampling rates of 256 kHz, a −3 dB bandwidth of 3 kHz.

(58) The pre-filter stage 21 provides amplification while filtering out high-frequency components that can cause aliasing effects (antialiasing pre-filter).

(59) The suppression filter stage 22 performs a suppression of the artifacts by cutting off frequencies above the interested frequency band (2-40 Hz). It is, preferably, implemented as a seventh order fully-differential switched capacitor low-pass filter. More preferably, the suppression filter stage 22 is implemented as elliptic ladder filter operating at 32 kHz and with a cut-off frequency of 40 Hz. Its transfer function is characterized by an attenuation of −52 dB at 130 Hz.

(60) FIGS. 8a-8d are graphs conceptually illustrating the frequency components of a signal at various stages within the front-end block 27. In particular, FIG. 8a illustrates the frequency components of input signal (V.sub.1a-V.sub.2a) which comprises both the neural signal 40 located at baseband and the harmonics of the stimulus artifact 41.

(61) FIG. 8b illustrates the frequency components of input signal 40,41 sampled at the first clock frequency F.sub.clock_PreFilter of the pre-filter stage 21. In FIG. 8b, the frequency components of the sampled input signal 42 (generated through sampling at the first clock frequency F.sub.clock_PreFilter) are represented at the first clock frequency F.sub.clock_PreFilter only. The frequency components of the 1/f noise 43 are represented superimposed to the neural component 40 of the original input signal at the baseband frequency. FIG. 8b also shows the first cut-off frequency F.sub.cut_PreFilter of the pre-filter stage 21.

(62) The frequency components of the 1/f noise 43 are removed by the pre-filter stage 21 through correlated double sampling, namely through double sampling of the signal such that the second sample—which is the one bearing noise related to itself for stationary reasons—is subtracted from the first sample. In terms of frequency response, this results in a high pass filtering (not represented) that only acts on the 1/f noise 43 but not on the input signal 42.

(63) FIG. 8c illustrates the frequency components downstream from the pre-filter stage 21 (intermediate signal) and sampled at the second clock frequency F.sub.clock_SuppFilter of the suppression filter stage 22. In FIG. 8c, again, the frequency components of the sampled intermediate signal 44 (generated through sampling at the second clock frequency F.sub.clock_SuppFilter) are represented at the second clock frequency F.sub.clock_SuppFilter only and the second cut-off frequency F.sub.cut_SuppFilter of the suppression filter stage 22 is also shown. From FIG. 8c, it is clear that the pre-filter 21 attenuates the frequency components of the sampled input signal 42 repeated every multiple of the sample frequency that were located outside of the passband (0 Hz-F.sub.cut_PreFilter) of the pre-filter 21 shown in FIG. 8b.

(64) FIG. 8d is a graph that illustrates the frequency components of the output signal (V.sub.1out-V.sub.2out) ideally comprising only the neural signal component 40. FIG. 8d shows that the suppression filter 22 attenuates the frequency components from the stimulus artifact 41 and the frequency component of the modulated intermediate signal 44 located outside of the passband (0 Hz-F.sub.cut_SuppFilter) of the suppression filter 22 shown in FIG. 8c.

(65) FIG. 9a and FIG. 9b show the effect of the acquisition module 20, namely provided with a multi-stage fully-differential switched capacitor integrated front-end block 21 configured for discrete-time signal processing (FIG. 9b), compared to a prior art single-ended analog front-end (FIG. 9a). In detail, from a comparison of the two figures a relevant reduction of the power mismatch due to residual stimulation interferences appears evident.

(66) The broadband spectral content of the stimulus artifact is theoretically infinite. For any finite sampling rate, this turns into unavoidable aliasing effects which could be reduced by increasing the sampling frequency. However, this would negatively affect the power consumption, which is not acceptable for wearable and/or implantable devices.

(67) Accordingly, in the A/D converter block 23 a first sampling stage 28 with high sampling rate (preferably at least of 32 kHz) is followed by a filter stage 29 for removing the quantization noise and a decimation stage 30, as shown in FIG. 2d.

(68) The sampling stage 28 comprises a single-bit, third-order, discrete-time delta-sigma (DT-ΔΣ) modulator.

(69) The filter stage 29, being a low-pass filter, is designed to further suppress the residual stimulation interferences, by setting the cut-off frequency at a value smaller than the stimulation frequency.

(70) The first sampling stage 28 of the A/D converter block 23 includes an amplification sub-stage (not illustrated) before the analog-to-digital conversion to adjust the dynamic range of the signal. The A/D converter block 23 has a differential signal as input and provides a digital data at the output.

(71) As shown in FIG. 2b, the acquisition module 20 may optionally comprise an input switch module, a low-pass filter module, and a high-pass filter module 24, 25, 26.

(72) The input switch module 24 may be in communication with the stimulation module 16. For example, the stimulation module 16 may generate and transmit a synchronization signal 24a to the input switch module 24, which may indicate whether to connect the input V.sub.1a and V.sub.2a to a reference voltage 17 or to leave them disconnected from the recording system during the stimulation. This module 24 provides for a synchronization with the stimulation module 16 or uses the electric stimulus itself in order to be able to disconnect the inputs of the front-end block 27 during stimulus. Disconnecting or grounding the inputs during each stimulus and re-connecting them to the recording system after each stimulation pulse provides for an additional suppression/mitigation of the stimulus artifact, thus unburdening the attenuation requirements at the level of the second suppression filter stage 22.

(73) The opening and closing of the Input Switch module 24 may introduce fluctuations characterized by high frequency frequencies which are removed or mitigated using a second functional module 25 which implements a low-pass filter.

(74) Furthermore, a third functional module 26 provides for high-pass filtering so as to eliminate the DC common mode voltages (before the Input Switch 24) and the DC differential components produced at the interface of the electrode and the brain.

(75) The apparatuses and methods described herein provide a solution for implantable neurostimulator devices requiring for ultra-low power features while being constrained by circuit dimensions.

(76) Implementing a multi-stage (e.g. two stage) front end block using fully-differential switched capacitor integrators configured for discrete-time signal processing (e.g. implementing the correlated double sampling technique) represent a unique solution to record neural signals—namely signal characterized by low amplitudes (<1 μV) at very low frequencies (1-40 Hz)—in presence of the stimulus artifact (usually having an amplitude of tens of mV).

(77) The fully-differential configuration of the front-end block 27 together with the specific design of the basic building units (e.g. the ones of FIG. 3 or of FIG. 6) based on which the pre-filter stage and the suppression filter stage of the front-end block are built, ensures a high CMRR.

(78) Moreover, the basic building units of FIG. 6 which allow the implementation of the correlated double sampling technique permits to achieve a high DC offset and 1/f noise rejection.

(79) Not least, switching capacitors circuits allow for low power and low size implementation.

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