FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS

Abstract

A flash memory storage apparatus includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line and including memory cells; each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array and configured to output a bias voltage to the word line. A first voltage is applied to a selected word line. A second voltage and a third voltage are applied to unselected second and third word lines, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the first word line. A biasing method of a flash memory storage apparatus is also provided.

Claims

1. A biasing method of a flash memory storage apparatus, wherein a memory cell array comprises at least one memory cell string coupled to between a bit line and a source line, the at least one memory cell string comprises a plurality of memory cells, and each of the memory cell is coupled to a corresponding word line, the biasing method comprising: applying a first voltage of bias voltages to a selected first word line of the word lines; and applying a second voltage of the bias voltages to an unselected second word line of the word lines and applying a third voltage of the bias voltages to a plurality of unselected third word lines of the word lines, wherein a value of the first voltage is greater than a value of the second voltage, the value of the second voltage is greater than a value of the third voltage, and the second word line and the plurality of third word lines are respectively located on two sides of the first word line, wherein the second word line is located at a source side area between the first word line and the source line, and the plurality of third word lines are located at a drain side area between the first word line and the bit line, wherein the plurality of third word lines comprise all unselected word lines located in the drain side area.

2. The biasing method of the flash memory storage apparatus according to claim 1, wherein the source side area comprises a plurality of unselected word lines, and the second voltage is applied to the second word line located closest to the first word line.

3. The biasing method of the flash memory storage apparatus according to claim 2, further comprising: applying a fourth voltage to the unselected word lines other than the second word line in the source side area, wherein the fourth voltage is less than the second voltage but greater than the third voltage.

4. The biasing method of the flash memory storage apparatus according to claim 1, further comprising: applying a system voltage to the bit line and the source line.

5. The biasing method of a flash memory storage apparatus according to claim 1, wherein the flash memory storage apparatus is a NAND gate flash memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0023] FIG. 1 is a schematic diagram briefly illustrating a flash memory storage apparatus according to an embodiment of the disclosure.

[0024] FIG. 2 is a schematic diagram briefly illustrating the memory cell string according to the embodiment depicted in FIG. 1.

[0025] FIG. 3 is a schematic diagram briefly illustrating a bias voltage applied to each driver line in a memory cell array according to an embodiment of the disclosure.

[0026] FIG. 4 is a schematic diagram briefly illustrating a bias voltage applied to each driver line in a memory cell array according to another embodiment of the disclosure.

[0027] FIG. 5 is a flow chart illustrating steps of a biasing method of a flash memory storage apparatus according to an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

[0028] FIG. 1 is a schematic diagram briefly illustrating a flash memory storage apparatus according to an embodiment of the disclosure. FIG. 2 is a schematic diagram briefly illustrating the memory cell string according to the embodiment depicted in FIG. 1. With reference to FIG. 1 and FIG. 2, a flash memory storage apparatus 100 provided in the embodiment includes a memory cell array 110 and a voltage generating circuit 120. The voltage generating circuit 120 is coupled to the memory cell array 110. In this embodiment, the flash memory storage apparatus 100 is, for instance, a NAND gate flash memory. The voltage generating circuit 120 may have a circuit design method well known to those skilled in the art.

[0029] The memory cell array 110 includes a bit line BL, a source line SL, and word lines WL0 to WL31. The memory cell array 110 further includes at least one memory cell string 122. The memory cell string 122 is coupled between the bit line BL and the source line SL. The memory cell string 122 includes a plurality of memory cells M0 to M30 and M31. The memory cells M0 to M30 and M31 are coupled to the corresponding word lines WL0 to WL30 and WL31. For instance, the memory cell M31 is coupled to the word line WL31, and the memory cell M0 is coupled to the word line WL0. The coupling relationship between other memory cells and their corresponding word lines may be deduced from FIG. 2 and thus will not be further described hereinafter. In addition, the number of the memory cell string, the number of the memory cells, and the number of the word lines do not serve to pose any limitation in the disclosure.

[0030] In this embodiment, the memory cell array 110 further includes selection transistors 121 and 123, which are respectively coupled to the corresponding selection lines SGD and SGS. The memory cell string 122 is coupled between the selection transistors 121 and 123. The selection transistors 121 and 123 are configured to select the memory cell string to be programmed during programming. In this embodiment, the memory cell array 110 further includes dummy memory cells 125 and 127, which are respectively coupled to the corresponding dummy word lines DWL. In an embodiment, the memory cell array 110 may not include any dummy memory cell nor any dummy word line.

[0031] FIG. 3 is a schematic diagram briefly illustrating a bias voltage applied to each driver line in a memory cell array according to an embodiment of the disclosure. With reference to FIG. 1 to FIG. 3, the voltage generating circuit 120 is configured to output a bias voltage V to the word lines WL0 to WL31 during the programming period. The bias voltage V includes a first voltage Vww, a second voltage Vpass_s, a third voltage Vpass_d, and a fourth voltage Vpass. The first voltage Vww is greater than the second voltage Vpass_s, and the second voltage Vpass_s is greater than the third voltage Vpass_d. The fourth voltage Vpass is less than the second voltage Vpass_s but is greater than the third voltage Vpass_d. In this embodiment, the first voltage Vww is applied to the selected word line WL28 (the first word line) of the word lines WL0 to WL31, and the second voltage Vpass_s and the third voltage Vpass_d are applied to the unselected word lines WL27, WL29 to WL31. In FIG. 3, the vertical height of the histogram represents the voltage applied to each driver line.

[0032] Specifically, among the word lines WL0 to WL31, the word line WL28 is, for instance, the selected word line. The other word lines WL0 to WL27 (the second word lines) and word lines WL29 to W31 (the third word lines) are unselected word lines. In this embodiment, compared to the first word line WL28, the second word lines WL0 to WL27 are located closer to the source line SL, wherein the word line WL27 is located closest to the first word line WL28. Compared to the first word line WL28, the third word lines WL29 to W31 are located closer to the bit line BL, wherein the word line WL29 is located closest to the first word line WL28.

[0033] In this embodiment, the second voltage Vpass_s is applied to the second word line WL27 located closest to the first word line WL28, and the fourth voltage Vpass is applied to the other second word lines WL0 to WL26; here, the fourth voltage Vpass is less than the second voltage Vpass_s. In this embodiment, since the voltage generating circuit 120 applies the second voltage Vpass_s to one single second word line WL27 located in a source side area and closest to the first word line WL28, and the second voltage Vpass_s is greater than the fourth voltage Vpass, the programming speed may be improved. In this embodiment, the second voltage Vpass_s is applied only to one single second word line WL27 located closest to the first word line WL28, which should however not be construed as a limitation in the disclosure. In an embodiment, the voltage generating circuit 120 may also apply the second voltage Vpass_s to one or more second word lines between the source line SL and the first word line WL28.

[0034] On the other hand, in this embodiment, the third voltage Vpass_d is applied to the third word lines WL29 to W31 between the bit line BL and the first word line WL28. Since the voltage generating circuit 120 provided in this embodiment applies the third voltage Vpass_d to all the third word lines WL29 to W31 in a drain side area, the gate induced drain leakage (GIDL) of the drain side area may be reduced.

[0035] In addition, in this embodiment, during the programming period, a system voltage VCC is applied to the bit line BL, the source line SL, and the selection line SGD, a ground voltage GND is applied to the selection line SGS, and a dummy voltage VDWL is applied to the dummy word line DWL. According to this embodiment, the system voltage VCC is equal to the dummy voltage VDWL, and the system voltage VCC is less than the third voltage Vpass_d. The system voltage VCC and the dummy voltage VDWL may be supplied by the voltage generating circuit 120 or other circuits in the apparatus.

[0036] In this embodiment, the third voltage Vpass_d is applied to all the third word lines WL29 to W31 between the bit line BL and the first word line WL28, which should however not be construed as a limitation in the disclosure. In an embodiment, the voltage generating circuit 120 may also apply the third voltage Vpass_d only to at least one third word line.

[0037] FIG. 4 is a schematic diagram briefly illustrating a bias voltage applied to each driver line in a memory cell array according to another embodiment of the disclosure. With reference to FIG. 1, FIG. 2, and FIG. 4, in this embodiment, the third voltage Vpass_d is applied to the third word line WL29 closest to the first word line WL28, and the fourth voltage Vpass is applied to the other third word lines WL30 and WL31 to reduce the GIDL of the drain side area.

[0038] FIG. 5 is a flow chart illustrating steps of a biasing method of a flash memory storage apparatus according to an embodiment of the disclosure. With reference to FIG. 1 to FIG. 3 and FIG. 5, the operating method provided in this embodiment is at least adapted to the flash memory storage apparatus 100 depicted in FIG. 1, which should however not be construed as a limitation in the disclosure. The flash memory storage apparatus 100 depicted in FIG. 1 is taken as an example; in step S100, the voltage generating circuit 120 applies the first voltage Vww to the selected first word line WL28 of the word lines. In step S110, the voltage generating circuit 120 applies the second voltage Vpass_s to at least one unselected second word line WL27 and applies the third voltage Vpass_d to at least one unselected third word line WL29. In step S120, the voltage generating circuit 120 applies the fourth voltage Vpass to all other unselected word lines. The first voltage Vww is greater than the second voltage Vpass_s, and the second voltage Vpass_s is greater than the third voltage Vpass_d. The fourth voltage Vpass is less than the second voltage Vpass_s but is greater than the third voltage Vpass_d. In addition, the teachings, suggestions, and implementations of the biasing method provided in this embodiment may be sufficiently obtained from the descriptions of the embodiments depicted in FIG. 1 to FIG. 4 embodiments.

[0039] To sum up, in one or more embodiments of the disclosure, the voltage generating circuit outputs an asymmetric bias voltage to the unselected word lines adjacent to the selected word line during programming, which not only reduces the GIDL and improves the reliability of the memory cells but also increases the programming speed.

[0040] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiment without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations, provided that they fall within the scope of the following claims and their equivalents.