Three-dimensional semiconductor wafer

Abstract

A three-dimensional semiconductor wafer relates to a semiconductor wafer, including a raw semiconductor wafer, at least one connection layer, a conduction layer and a protection layer, wherein the protection layer is arranged on the conduction layer; the connection layer is inserted into a bottom surface or/and a top surface of the raw semiconductor wafer; and the conduction layer is arranged on the bottom surface of the raw semiconductor wafer.

Claims

1. A three-dimensional semiconductor wafer, comprising a raw semiconductor wafer, a connection layer, a conduction layer and a protection layer, wherein the protection layer is arranged on the conduction layer; the connection layer is inserted into a bottom surface or/and a top surface of the raw semiconductor wafer; and the conduction layer is arranged on the bottom surface of the raw semiconductor wafer.

2. The three-dimensional semiconductor wafer, as recited in claim 1, wherein the raw semiconductor wafer is cylindrical.

3. The three-dimensional semiconductor wafer, as recited in claim 1, wherein an amount of the connection layer is at least one.

4. The three-dimensional semiconductor wafer, as recited in claim 1, wherein the connection layer comprises a plurality of connection parts; a first end of each connection part is inserted into the raw semiconductor wafer, and a second end of each connection part is level with the bottom surface or the top surface of the raw semiconductor wafer; the connection parts are prismatic, cylindrical, spherical or ellipsoidal; and the connection parts are arranged inside the raw semiconductor wafer in a form of array.

5. The three-dimensional semiconductor wafer, as recited in claim 3, wherein the connection layer comprises a plurality of connection parts; a first end of each connection part is inserted into the raw semiconductor wafer, and a second end of each connection part is level with the bottom surface or the top surface of the raw semiconductor wafer; the connection parts are prismatic, cylindrical, spherical or ellipsoidal; and the connection parts are arranged inside the raw semiconductor wafer in a form of array.

6. The three-dimensional semiconductor wafer, as recited in claim 1, wherein the protection layer is arranged on an outer surface of the conduction layer.

7. The three-dimensional semiconductor wafer, as recited in claim 4, wherein: the raw semiconductor wafer is defined as an N.sup.− region, which has a conduction type of N-type; the connection layer is defined as an N.sup.+ region, which has the conduction type of N-type; for the array-distributed connection parts, first ends are inserted into the raw semiconductor wafer, and second ends are connected to each other on the bottom surface of the raw semiconductor wafer through the conduction layer; the conduction layer is defined as the N.sup.+ region, which has the conduction type of N-type; and the protection layer is arranged on the conduction layer at the bottom surface of the raw semiconductor wafer.

8. The three-dimensional semiconductor wafer, as recited in claim 4, wherein: the raw semiconductor wafer is defined as an N.sup.− region, which has a conduction type of N-type; the connection layer is defined as a P.sup.+ region, which has a conduction type of P-type; for the array-distributed connection parts, first ends are inserted into the raw semiconductor wafer, and second ends are connected to each other on the bottom surface of the raw semiconductor wafer through the conduction layer; the conduction layer is defined as the P.sup.+ region, which has the conduction type of P-type; and the protection layer is arranged on the conduction layer at the bottom surface of the raw semiconductor wafer.

9. The three-dimensional semiconductor wafer, as recited in claim 4, wherein: the raw semiconductor wafer is defined as an N.sup.− region, which has a conduction type of N-type; the connection layer defined as a P.sup.+ region, which has a conduction type of P-type; for the array-distributed connection parts, first ends are inserted into the raw semiconductor wafer, and second ends are connected to each other on the bottom surface of the raw semiconductor wafer through the conduction layer; the conduction layer is defined as an N.sup.+ region, which has the conduction type of N-type; and the protection layer is arranged on the conduction layer at the bottom surface of the raw semiconductor wafer.

10. The three-dimensional semiconductor wafer, as recited in claim 4, wherein: the raw semiconductor wafer is defined as an N.sup.− region, which has a conduction type of N-type; the connection layer is defined as a P.sup.+ region, which has a conduction type of P-type; for the array-distributed connection parts, first ends are inserted into the raw semiconductor wafer, and second ends are level with the top surface of the raw semiconductor wafer; the conduction layer is defined as an N.sup.+ region, which has the conduction type of N-type; and the protection layer is arranged on the conduction layer at the bottom surface of the raw semiconductor wafer.

11. The three-dimensional semiconductor wafer, as recited in claim 1, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

12. The three-dimensional semiconductor wafer, as recited in claim 2, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

13. The three-dimensional semiconductor wafer, as recited in claim 3, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

14. The three-dimensional semiconductor wafer, as recited in claim 4, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

15. The three-dimensional semiconductor wafer, as recited in claim 5, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

16. The three-dimensional semiconductor wafer, as recited in claim 6, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

17. The three-dimensional semiconductor wafer, as recited in claim 7, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

18. The three-dimensional semiconductor wafer, as recited in claim 8, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

19. The three-dimensional semiconductor wafer, as recited in claim 9, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

20. The three-dimensional semiconductor wafer, as recited in claim 10, wherein the protection layer is connected to the conduction layer and the protection layer is a SiO.sub.2 layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is an exploded view of a three-dimensional semiconductor wafer according to preferred embodiments of the present invention.

[0014] FIG. 2 is an exploded view of an (N.sup.−/N.sup.+/N.sup.+)-typed three-dimensional semiconductor wafer according to a first preferred embodiment of the present invention.

[0015] FIG. 3 is an exploded view of an (N.sup.−/P.sup.+/P.sup.+)-typed three-dimensional semiconductor wafer according to a second preferred embodiment of the present invention.

[0016] FIG. 4 is an exploded view of an (N.sup.−/N.sup.+/P.sup.+)-typed three-dimensional semiconductor wafer according to a third preferred embodiment of the present invention.

[0017] FIG. 5 is an exploded view of an (N.sup.−/P.sup.+/N.sup.+)-typed three-dimensional semiconductor wafer according to a fourth preferred embodiment of the present invention.

[0018] FIG. 6 is an exploded view of a (P.sup.−/P.sup.+/P.sup.+)-typed three-dimensional semiconductor wafer according to a fifth preferred embodiment of the present invention.

[0019] FIG. 7 is an exploded view of a (P.sup.−/N.sup.+/N.sup.+)-typed three-dimensional semiconductor wafer according to a sixth preferred embodiment of the present invention.

[0020] FIG. 8 is an exploded view of an (N.sup.−/P.sup.+ top surface/N.sup.+)-typed three-dimensional semiconductor wafer according to a seventh preferred embodiment of the present invention.

[0021] FIG. 9 is an exploded view of an (N.sup.−/P.sup.+ top surface/N.sup.+ bottom surface/N.sup.+)-typed three-dimensional semiconductor wafer according to an eighth preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0022] A three-dimensional semiconductor wafer comprises a raw semiconductor wafer 1, at least one connection layer, a conduction layer 3 and a protection layer 4, wherein: the protection layer 4 is arranged on the conduction layer 3; the connection layer is inserted into a bottom surface or/and a top surface of the raw semiconductor wafer 1; the conduction layer is arranged on the bottom surface of the raw semiconductor wafer 1; the raw semiconductor wafer 1 is cylindrical; the connection layer comprises a plurality of connection parts 2; a first end of each connection part 2 is inserted into the raw semiconductor wafer 1, and a second end of each connection part 2 is level with the bottom surface or the top surface of the raw semiconductor wafer 1; the connection parts 2 are prismatic, cylindrical, spherical or ellipsoidal; the connection parts 2 are arranged inside the raw semiconductor wafer 1 in a form of array; and the protection layer 4 is arranged on an outer surface of the conduction layer 3.

[0023] For the three-dimensional semiconductor wafer provided by the present invention, according to types of semiconductors of different power, a conduction type of the raw semiconductor wafer 1, the connection layer, and the conduction layer 3 can be respectively selected as N-type or P-type, wherein the bottom surface of the raw semiconductor wafer 1 can be produced according to requirements of a chip.

First Preferred Embodiment

[0024] As shown in FIG. 2, the raw semiconductor wafer 1 is a lightly doped N-type region, namely an N.sup.− region; the connection layer is a heavily doped N-type region, namely an N.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped N-type region, namely the N.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1.

Second Preferred Embodiment

[0025] As shown in FIG. 3, the raw semiconductor wafer 1 is a lightly doped N-type region, namely an N.sup.− region; the connection layer is a heavily doped P-type region, namely a P.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped P-type region, namely the P.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1.

Third Preferred Embodiment

[0026] As shown in FIG. 4, the raw semiconductor wafer 1 is a lightly doped N-type region, namely an N.sup.− region; the connection layer is a heavily doped N-type region, namely an N.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped P-type region, namely a P.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1.

Fourth Preferred Embodiment

[0027] As shown in FIG. 5, the raw semiconductor wafer 1 is a lightly doped N-type region, namely an N.sup.− region; the connection layer is a heavily doped P-type region, namely a P.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped N-type region, namely an N.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1. The above three-dimensional semiconductor wafer is mainly applicable in production of N-channel enhancement mode metal-oxide-semiconductor field-effect transistor (MOSFET) and fast recovery diode (FRD) chip.

Fifth Preferred Embodiment

[0028] As shown in FIG. 6, the raw semiconductor wafer 1 is a lightly doped P-type region, namely a P.sup.− region; the connection layer is a heavily doped P-type region, namely a P.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped P-type region, namely the P.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1. The above three-dimensional semiconductor wafer is mainly applicable in production of P-channel enhancement mode MOSFET and giant transistor (GTR).

Sixth Preferred Embodiment

[0029] As shown in FIG. 7, the raw semiconductor wafer 1 is a lightly doped P-type region, namely a P.sup.− region; the connection layer is a heavily doped N-type region, namely an N.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped N-type region, namely the N.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1.

Seventh Preferred Embodiment

[0030] As shown in FIG. 8, the raw semiconductor wafer 1 is a lightly doped N-type region, namely an N.sup.− region; the connection layer is a heavily doped P-type region, namely a P.sup.+ region; for the array-distributed connection parts 2, the first ends are inserted into the raw semiconductor wafer 1, and the second ends are level with the top surface of the raw semiconductor wafer 1; the conduction layer 3 is a heavily doped N-type region, namely an N.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1.

Eighth Preferred Embodiment

[0031] As shown in FIG. 9, the raw semiconductor wafer 1 is a lightly doped N-type region, namely an N.sup.− region; a first connection layer at the top surface of the raw semiconductor wafer is a heavily doped P-type region, namely a P.sup.+ region, and the array-distributed connection parts 2 of the first connection layer have the first ends inserted into the raw semiconductor wafer 1 and the second ends level with the top surface of the raw semiconductor wafer 1; a second connection layer at the bottom surface of the raw semiconductor wafer 1 is a heavily doped N-type region, namely an N.sup.+ region, and the array-distributed connection parts 2 of the second connection layer have the first ends inserted into the raw semiconductor wafer 1 and the second ends connected to each other on the bottom surface of the raw semiconductor wafer 1 through the conduction layer 3; the conduction layer 3 is a heavily doped N-type region, namely the N.sup.+ region; and the protection layer 4 is arranged on the conduction layer 3 at the bottom surface of the raw semiconductor wafer 1.