THIN FILM TRANSISTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME

Abstract

A thin film transistor (TFT) structure is provided herein, which comprises a substrate, a light-shielding resin, a polysilicon, a gate electrode insulator, a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode. The light-shielding resin has functions of light-shielding and insulation. With doping through two through holes at two sides, the manufacturing process is simplified, the exposure process is simplified, the production time is shortened, the usage of masks is decreased, and the production cost is lowered.

Claims

1. A Thin Film Transistor (TFT) structure, comprising: a substrate; a light-shielding resin, disposed on the substrate; a polysilicon, disposed on the light-shielding resin; a gate electrode insulator, disposed on the substrate and the polysilicon; a gate electrode, disposed close to the gate electrode insulator; an interlayer dielectric layer, disposed on the gate electrode insulator and the gate electrode; a source electrode and a drain electrode, disposed on the interlayer dielectric layer; wherein the source electrode and the drain electrode are respectively connected with the polysilicon via two through holes; the polysilicon comprises a channel-doping region and two through-hole-doping regions; the through-hole-doping regions and the two through holes connect with each other and complete doping by the two through holes; the source electrode and the drain electrode are connected with the through-hole-doping regions on two sides of the channel-doping region by the two through holes.

2. The TFT structure according to claim 1, wherein the through holes penetrate the interlayer dielectric layer and a portion of the gate electrode insulator.

3. The TFT structure according to claim 1, wherein the light-shielding resin comprises an epoxy resin or polyurethane.

4. The TFT structure according to claim 1, further comprising: a planar, disposed on a portion of the source electrode and the drain electrode, and overlapping the interlayer dielectric layer; and a transparent conduction layer, disposed on the planar and another portion of the source electrode and the drain electrode.

5. A Thin Film Transistor (TFT) structure, comprising: a substrate; a light-shielding resin, disposed on the substrate; a polysilicon, disposed on the light-shielding resin; a gate electrode insulator, disposed on the substrate and the polysilicon; a gate electrode, disposed close to the gate electrode insulator; an interlayer dielectric layer, disposed on the gate electrode insulator and the gate electrode; a source electrode and a drain electrode, disposed on the interlayer dielectric layer; wherein the source electrode and the drain electrode are respectively connected with the polysilicon by two through holes.

6. The TFT structure according to claim 5, wherein the through holes penetrate the interlayer dielectric layer and a portion of the gate electrode insulator.

7. The TFT structure according to claim 5, wherein the light-shielding resin comprises an epoxy resin or polyurethane.

8. The TFT structure according to claim 5, further comprising: a planar, disposed on a portion of the source electrode and the drain electrode, and overlapping the interlayer dielectric layer; and a transparent conduction layer, disposed on the planar and another portion of the source electrode and the drain electrode.

9. The TFT structure according to claim 5, wherein the polysilicon comprises a channel-doping region and two through-hole-doping regions, the through-hole-doping regions and the two through holes connect with each other and complete doping by the two through holes, the source electrode and the drain electrode are connected with the through-hole-doping regions on two sides of the channel-doping region by the two through holes.

10. A TFT structure manufacturing method, comprising: disposing a substrate; depositing a resin layer on the substrate, and forming a light-shielding resin by using a first mask; depositing a polysilicon layer, and forming a polysilicon on the light-shielding resin by using a second mask; performing a first doping to the polysilicon; depositing a gate electrode insulator on the substrate and the polysilicon; depositing a first metal layer, and using a third mask to form a gate electrode on the gate electrode insulator; depositing an interlayer dielectric layer on the gate electrode insulator and the gate electrode; using a fourth mask to form two through holes in the interlayer dielectric layer and a portion of the gate electrode insulator; and depositing a second metal layer, and using a fifth mask to form a source electrode and a drain electrode on the interlayer dielectric layer; wherein the source electrode and the drain electrode are respectively connected with the polysilicon by two through holes.

11. The TFT structure manufacturing method according to claim 10, wherein a doping to the polysilicon comprises the first doping and a second doping: the first doping is performed on the polysilicon after forming the polysilicon and before depositing the gate electrode insulator; and the second doping is performed on the polysilicon through the two through holes after forming the two through holes.

12. The TFT structure manufacturing method according to claim 11, wherein the polysilicon is completely doped in the first doping.

13. The TFT structure manufacturing method according to claim 11, wherein a channel-doping region of the polysilicon is doped and through-hole-doping regions on two sides of the channel-doping region are not doped under the protection of the mask in the first doping.

14. The TFT structure manufacturing method according to claim 12, wherein the through-hole-doping regions connected to the two through holes are doped through the two through holes in the second doping, so that the polysilicon forms the channel-doping region and the through-hole-doping regions on two sides of the channel-doping region.

15. The TFT structure manufacturing method according to claim 13, wherein the through-hole-doping regions connected to the two through holes are doped through the two through holes in the second doping, so that the polysilicon forms the channel-doping region and the through-hole-doping regions on two sides of the channel-doping region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIGS. 1-5, 6-1, 6-2, and 7-18 are side view drawings of each manufacturing process of the thin film transistor (TFT) of the present invention;

[0020] FIG. 19 is a flowchart of a method of manufacturing the TFT structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following description of each embodiment, with reference to the accompanying drawings, is used to exemplify specific embodiments which may be carried out in the present invention. Directional terms mentioned in the present invention, such as “top”, “bottom”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only used with reference to the orientation of the accompanying drawings. Therefore, the used directional terms are intended to illustrate, but not to limit, the present invention.

[0022] Please refer to FIG. 18, which is a side view drawing of the thin film transistor (TFT) structure 100 of the present invention. The TFT structure 100 comprises a substrate 110, a light-shielding resin 120, a polysilicon 130, a gate electrode insulator 140, a gate electrode 150, an interlayer dielectric layer 160, a source electrode 172, a drain electrode 171, a planar 180, and a transparent conduction layer 190.

[0023] The light-shielding resin 120 is disposed on the substrate 110. In detail, the light-shielding resin 120 comprises an epoxy resin or polyurethane. The light-shielding resin 120 can not only shielding light but also serve as an insulation layer.

[0024] The polysilicon 130 is disposed on the light-shielding resin 120. The polysilicon 130 is used to provide electrons and holes for conduction. In detail, an area of the polysilicon 130 and an area of the light-shielding resin 120 are the same (perpendicular with the light's direction). The polysilicon 130 comprises a channel-doping region 133 and two through-hole-doping regions (131, 132), the through-hole-doping regions (131, 132) and the two through holes 170 connect with each other and complete doping by the two through holes 170, the source electrode 172 and the drain electrode 171 are connected with the through-hole-doping regions (131, 132) on two sides of the channel-doping region 133 by the two through holes 170.

[0025] The gate electrode insulator 140 is disposed on the substrate 110 and the polysilicon 130. In detail, the light-shielding resin 120 is disposed on a region where the polysilicon 130 and the gate electrode 150 are disposed, to avoid making the polysilicon generate a light leakage current. In other words, an area of the light-shielding resin 120 is larger than or equal to an area of the polysilicon 130 (perpendicular with the light's direction). The first metal layer 155 used to form the gate electrode 150 can be molybdenum. Referring to FIGS. 8-9, the gate electrode 150 are formed by using a third mask on the first metal layer 155. The gate electrode insulator has high dielectric constant.

[0026] The interlayer dielectric layer 160 is disposed on the gate electrode insulator 140 and the gate electrode 150. In detail, the interlayer dielectric layer 160 completely covers the gate electrode 150 and other regions. The interlayer dielectric layer 160 is used to lower the capacitance value between the multi-layer wires. Generally, laminated layers of oxidized silicon-silicon nitride-oxidized silicon or laminated layers of oxidized silicon-silicon nitride are used to be flash memory of the interlayer dielectric layer 160.

[0027] The through holes 170 penetrate the interlayer dielectric layer 160 and a portion of the gate electrode insulator 140. In detail, two through holes 170 penetrate the gate electrode insulator 140 and the interlayer dielectric layer 160. For the two through holes 170 are deposited with the same material, the source electrode 172 and the drain electrode 171 respectively connect with two sides of the polysilicon 130.

[0028] In the preferred embodiment, the drain electrode 171 and the source electrode 172 are disposed on the interlayer dielectric layer 160. However, in different preferred embodiments, the drain electrode 171 and the source electrode 172 can change position. A second metal layer used to form the drain electrode 171 and the source electrode 172 can be molybdenum/aluminum/molybdenum.

[0029] The planar 180 is disposed on a portion of the drain electrode 171 and the source electrode 172, and overlapping the interlayer dielectric layer 160. In the preferred embodiment, the planar 180 completely overlaps the source electrode 172, however, only partially overlaps the drain electrode 171.

[0030] The transparent conduction layer 190 is disposed on the planar 180 and another portion of the drain electrode 171 and the source electrode 172. In the preferred embodiment, the transparent conduction layer 190 directly overlaps the drain electrode 171 which is not be overlapped by the planar 180. The transparent conduction layer 190 can be indium tin oxide.

[0031] A doping to the polysilicon 130 comprises the first doping and a second doping. The first doping is performed on the polysilicon 130 after forming the polysilicon 130 and before depositing the gate electrode insulator 140. The second doping is performed on the two through-hole-doping regions (131,132) of the polysilicon 130 through the two through holes 170 after forming the two through holes 170.

[0032] Please refer to FIGS. 1-19, FIGS. 1-18 are side view drawings of each manufacturing process of the TFT of the present invention. FIG. 19 is a flowchart of a method of manufacturing the TFT structure 100 according to the present invention. The method comprises:

[0033] Step S01: as shows in FIG. 1, a substrate 110 is disposed. The substrate 110 can be a glass substrate or a transparent plastic baseplate.

[0034] Step S02: as shows in FIG. 2, a resin layer 125 is deposited on the substrate 110. As FIG. 3 shows, the resin layer 125 is exposed and developed to form a light-shielding resin 120 by using a first mask 201.

[0035] Step S03: as shows in FIG. 4, a polysilicon layer 135 is deposited. As FIG. 5 shows, the polysilicon layer 135 is exposed and developed to form a polysilicon 130 on the light-shielding resin 120 by using a second mask 202.

[0036] Step S04: as shows in FIG. 6-1, a first doping is performed on the polysilicon 130 by using a first doping mask 208. In the preferred embodiment, the polysilicon 130 is whole and evenly doped.

[0037] In another preferred embodiment, as FIG. 6-2 shows, a first doping is performed on the polysilicon 130 by using a second doping mask 209. In the preferred embodiment, channel-doping region 133 of the polysilicon 130 is doped; through-hole-doping regions (131,132) on two sides of the channel-doping region are protected from doping during the mask process.

[0038] Step S05: as shows in FIG. 7, a gate electrode insulator 140 is deposited on the substrate 110 and the polysilicon 130. The gate electrode insulator 140 can be SiOx, SiNx, or a combination of both.

[0039] Step S06: as shows in FIG. 8, a first metal layer 155 is deposited by a chemical vapor deposition (CVD) or a vacuum evaporation (VE). As shows in FIG. 9, a third mask 203 is used to expose and develop the first metal layer 155, to form a gate electrode 150 on the gate electrode insulator 140. Generally, the first metal layer 155 can be molybdenum (Mo), aluminum (Al), aluminum alloy, titanium (Ti), copper (Cu), or wolfram (W).

[0040] Step S07: as shown in FIG. 10, an interlayer dielectric layer 160 is deposited on the gate electrode insulator 140 and the gate electrode 150.

[0041] Step S08: as shown in FIG. 11, a fourth mask 204 is used to expose and develop the interlayer dielectric layer 160 and the gate electrode insulator 140, to form two through holes 170 in the interlayer dielectric layer 160 and a portion of the gate electrode insulator 140.

[0042] Step S09: a second doping is performed on the polysilicon 130 through the two through holes 170. The through-hole-doping regions (131,132) are connected with the two through holes 170 and complete the second doping by the two through holes. With the second doping to the through-hole-doping regions (131,132), the polysilicon 130 forms the channel-doping region and the through-hole-doping regions (131,132) on two sides of the channel-doping region 133.

[0043] Step S10: as shown in FIG. 13, a second metal layer 175 is deposited by a chemical vapor deposition (CVD) or a vacuum evaporation (VE). As FIG. 14 shows, a fifth mask 205 is used to expose and develop the second metal layer 175, to form a drain electrode 171 and a source electrode 172 on the interlayer dielectric layer 160. For the second metal layer 175 fills the two through holes 170, the drain electrode 171 and the source electrode 172 are respectively connected with the polysilicon 130 by two through holes 170.

[0044] Step S11: as shown in FIG. 15, a planar 180 is deposited. As shows in FIG. 16, a sixth mask 206 is used to expose and develop the planar 180, to form the planar 180 only on a portion of the drain electrode 171 and the source electrode 172, and overlap the interlayer dielectric layer 160.

[0045] Step S12: as shown in FIG. 17, a transparent conduction layer 190 is deposited on the planar 180 and another portion of the drain electrode 171 and the source electrode 172.

[0046] Step S13: as shown in FIG. 18, a seventh mask 207 is used to expose and develop the transparent conduction layer 190, to form a notch on the drain electrode 171.

[0047] Although the present invention has been disclosed as preferred embodiments, the foregoing preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art, without departing from the spirit and scope of the present invention, can make various kinds of modifications and variations to the present invention. Therefore, the scope of the claims of the present invention must be defined.