METHOD AND APPRATUS FOR SEMICONDUCTOR PACKAGING

Abstract

A method of forming a package includes providing a die, which includes a substrate having a circuit, a first passivation layer on the substrate, a plurality of pads on the first passivation layer, and a second passivation layer disposed on the first passivation layer and covering the plurality of pads. The method also includes forming one or more trenches by etching the second passivation layer that overlies a portion of the first passivation layer on the outside of the plurality of pads, and forming an organic polymer overlying the die after the one or more trenches are formed, thereby forming the package.

Claims

1. A method of forming a package, comprising: providing a die, the die comprising: a substrate having a circuit; a first passivation layer on the substrate; a plurality of pads on the first passivation layer; and a second passivation layer disposed on the first passivation layer and covering the plurality of pads; forming one or more trenches by etching the second passivation layer that overlies a portion of the first passivation layer on the outside of the plurality of pads; and forming an organic polymer overlying the die after the one or more trenches are formed, thereby forming the package.

2. The method according to claim 1, wherein the plurality of pads comprises a first pad, the first pad being adjacent to an edge of the substrate, the first pad being closer to said edge of the substrate than other pads; wherein the one or more trenches are formed in the second passivation layer overlying a portion of the first passivation layer outside the first pad.

3. The method according to claim 2, wherein the one or more trenches are located at a preset distance from a protruding portion of the second passivation layer overlying the first pad.

4. The method according to claim 1, further comprising curing the organic polymer.

5. The method of claim 1, wherein the one or more trenches extend into the first passivation layer.

6. The method according to claim 1, wherein the first passivation layer comprises a first dielectric layer, a second dielectric layer, and the third dielectric layer, and wherein the method further comprises etching the first passivation layer using the second dielectric layer as an etch stop layer.

7. The method according to claim 1, wherein each of the one or more trenches is an annular trench surrounding the circuit.

8. The method according to claim 7, wherein the one or two trenches comprise at least two annular trenches.

9. The method according to claim 1, wherein said die further comprises a sealing structure around the circuit in the vicinity of the die edge, and the one or more trenches are located between the pad and the sealing structure.

10. The method according to claim 1, wherein the first passivation layer comprises a nitride layer and an oxide layer, and the second passivation layer comprises a nitride layer and an oxide layer.

11. A package, comprising: a die, the die comprising: a substrate having a circuit; a first passivation layer on the substrate; a plurality of pads on the first passivation layer; and a second passivation layer disposed on the first passivation layer and covering the plurality of pads; one or more trenches in the second passivation layer that overlies a portion of the first passivation layer on the outside of the plurality of pads; and an organic polymer overlying the die and filling the one or more trenches, thereby forming the package.

12. The package according to claim 11, wherein the plurality of pads comprises a first pad, the first pad being adjacent to an edge of the substrate, the first pad being closer to said edge of the substrate than other pads; wherein the one or more trenches are formed in the second passivation layer overlying a portion of the first passivation layer outside the first pad.

13. The package according to claim 12, wherein the one or more trenches are located at a preset distance from a protruding portion of the second passivation layer overlying the first pad.

14. The package of claim 11, wherein the first passivation layer comprises a first dielectric layer, a second dielectric layer, and the third dielectric layer, and the one or more trenches extend through the first dielectric layer and stop at the second insulating dielectric layer.

15. The package of claim 11, wherein the one or more trenches extend into the first passivation layer.

16. The package of claim 11, wherein each of the one or more trenches is an annular trench surrounding the circuit.

17. The package of claim 16, wherein the one or two trenches comprise at least two annular trenches.

18. The package of claim 11, wherein the die further comprises a sealing structure around the circuit in the vicinity of the die edge, and the one or more trenches are located between the pad and the sealing structure.

19. The package of claim 11, wherein the first passivation layer comprises a nitride layer and an oxide layer, and the second passivation layer comprises a nitride layer and an oxide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is a simplified flowchart illustrating a method for manufacturing a package according to an embodiment of the present invention.

[0028] FIG. 2 is a simplified cross-sectional diagram illustrating a view of a die according to an embodiment of the present invention.

[0029] FIG. 3A is a top view of a die including the trenches, and FIG. 3B is a cross-sectional view along the line A-A′ in FIG. 3A according to an embodiment of the present invention.

[0030] FIG. 4 is a cross-sectional view illustrating a trench formation according to another embodiment of the present invention.

[0031] FIG. 5 is a cross-sectional view illustrating polymer filling the trenches according to an embodiment of the present invention.

[0032] FIGS. 6A and 6B are cross-sectional view diagrams illustrating a curing process of the organic polymer according to a conventional process.

[0033] FIG. 7 is a cross-section view diagram illustrating a curing process of a die package according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0034] The drawings of various exemplary embodiments of the present invention will be described in detail. It should be noted that, unless otherwise specified, the relative arrangement set forth in these embodiments, components and steps, the numerical expressions, and values do not limit the scope of the present invention. At the same time, it should be appreciated that, for ease of description, the dimensions of the various parts are not illustrated in the drawings according to the actual proportional relationship.

[0035] The following description of exemplary embodiments is merely illustrative of the present invention and in no way intends to impose any restrictions on its use or application. Techniques, methods, and equipment known to someone of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the techniques, methods and equipment should be considered as part of the specification.

[0036] In all the examples shown and discussed, any specific value is to be construed as merely illustrative, and not as a limitation. Accordingly, another exemplary embodiment may have different values. It should be also noted that like reference numerals and letters refer to similar items in the following figures, and thus, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0037] In the package of semiconductor dies, the ball grid array is covered with a passivation layer, which in turn is covered by organic polymers (for example, epoxy or polyimide). The inventors have discovered that, during thermal treatment, the organic polymer layer is contracted, dragging up the passivation layer. On the other hand, the bonding pads under the passivation layer are expanded due to heat treatment, pressing against the passivation layer. Further, the inventors have identified that the stress on the passivation layer tends to concentrate near the step region or protruding region of the passivation layer at the edge of the pads. The thermal mismatch between the pads and the passivation layer can, in the passivation layer near the step region, cause fatigue, leading to cracking. Moreover, subsequent stability tests, for example, the unbiased highly accelerated stress test (uHAST), can further increase the cracking of the passivation layer. The cracks in the passivation layer can ultimately cause the bonding pads to be exposed. Embodiments of the present invention provide methods and devices that address the problems described above.

[0038] FIG. 1 is a simplified flowchart illustrating a method for manufacturing a package according to an embodiment of the present invention. The steps in this flowchart are further described below with reference to FIGS. 2-7.

[0039] As shown in FIG. 1, in step 101, the method includes providing a die. FIG. 2 is a simplified cross-sectional diagram illustrating a view of a die according to an embodiment of the present invention. As shown in FIG. 2, a die 200 includes a substrate 201, which may be a silicon substrate having a circuit or other semiconductor material substrates. Here, for clarity, the circuit is not shown in FIG. 2. Die 200 further includes a first passivation layer 202 on the substrate 201. In one embodiment, the first passivation layer 202 may include a stack of nitride layer 212 and oxide layer 222. For example, the first passivation layer 202 may include a plurality of nitride layer 212 (e.g., SiN) and oxide layer 222 (e.g., formed from TEOS, tetraethoxysilane). In another embodiment, the first passivation layer 202 may be formed by an oxide layer 222, a nitride layer 212, and an oxide layer 222 forming a three-layer stack. As a non-limiting example, the thickness of the nitride layer 212 may be about 750 Angstroms (Å), and the thickness of the oxide layer 222 may be about 4000 Å.

[0040] Die 200 can also include a plurality of bonding pads 203 on the first passivation layer 202. It is noted that FIG. 2 merely schematically shows a pad 203 as an example. Those skilled in the art will readily understand that a plurality of pads 203 may be distributed on the first passivation layer 202. In an embodiment, pad 203 may be an aluminum (Al) pad, and the thickness of pad 203 can be, for example, about 14.5 nm.

[0041] Die 200 can further include a second passivation layer 204 overlying the first passivation layer 202 and covering the plurality of pads 203. The second passivation layer 204 may include a stack of an oxide layer 214 and nitride layer 224. Oxide layer 214 may be an oxide formed from TEOS, and a nitride layer 224 is typically silicon nitride, SiN, for example. As a non-limiting example, the thickness of the oxide layer 214 may be about 4000 angstroms, and the thickness of the nitride layer 224 may be about 6000 angstroms. In an embodiment, the die 200 may also include a sealing structure 205 surrounding the circuit in the vicinity of the die edge, e.g., a seal ring.

[0042] Returning to FIG. 1, in step 103, the second passivation layer is etched to form trenches, which are located on the first passivation layer outside the plurality of die pads. FIG. 3A is a top view of die including the trenches, and FIG. 3B is a cross-sectional view along the line A-A′ in FIG. 3A according to an embodiment of the present invention. As shown in FIG. 3A, a plurality of pads may include a first pad 213, which is adjacent to a first edge of the substrate. Trenches 301 are formed in the second passivation layer 204 between the first pad 213 and the edge of the substrate. As shown, the trenches are formed outside the outmost pads of the die, i.e., between the outmost dies and the edge of the die.

[0043] In an embodiment, the groove or trenches 301 may be annular grooves or trenches around the circuit, shown in FIG. 3A. In some embodiments, there may be a single annular trench. In other embodiments, there may be at least two annular grooves or trenches 301, so that the interfacial area can be further increased between a subsequently formed organic polymer and the die surface. Further, in the case where the die includes a sealing structure 205, grooves 301 are formed between the pads 203 and the sealing structure 205.

[0044] As shown in FIG. 3B, grooves or trenches 301 are formed on the first passivation layer 202 outside of all pads 213. In other words, the etching of the second passivation layer is stopped on the first passivation layer. It is noted that the terms groove and trench are used interchangeably in this description. In FIG. 3B, dotted line 302 separates the second passivation layer into two regions. The first region, to the right of dotted line 302, the second passivation layer is disposed over the pads and is higher than the second region to the left of dotted line 302 which does not overlie the pads. In an embodiment, the trenches 301 are disposed at a certain distance away from dotted line 302.

[0045] FIG. 4 is a cross-sectional view illustrating a trench formation according to another embodiment of the present invention. As shown in FIG. 4, groove or grooves 301 may be extended into the first passivation layer 202. In one implementation, the first passivation layer 202 may be a laminated layer including a first dielectric layer (e.g., an oxide layer 222), a second dielectric layer (e.g., nitride layer 212) and a third dielectric layer (e.g., the oxide layer 222). Different dielectric layers in the first passivation layer can be used as an etch stop layer during the etching of the second passivation layer. The depth of etching can be selected such that grooves or trenches 301 can extend into the first passivation layer 202 at various depths, to further increase the interfacial area of the subsequently formed organic polymer in the die surface.

[0046] Referring to FIG. 1 again, in step 105. As shown in FIG. 5 an organic polymer 501 is formed to cover the die and extend into the trenches to thereby form the package. Organic polymer 501 may be, for example, a polyimide or an epoxy resin. In some embodiments, organic polymer 501 fills trenches 301. Thereafter, organic polymer 501 may undergo a curing treatment (e.g., thermal dehydration treatment).

[0047] FIGS. 6A and 6B are cross-sectional view diagrams illustrating a curing process of the organic polymer according to a conventional process. In FIG. 6A, the organic polymer 501 is shown to contract during a curing treatment. The shrinkage of organic polymer 501 causes stress on the second passivation layer 204, leading to deformation and/or a peeling edge. Further, pads 203 under the second passivation layer 203 may expand due to thermal expansion, so as to press the second passivation layer 204. This can lead to cracking in second passivation layer 204 in the vicinity of the stepped region near the pas 203. FIG. 6B is a cross-section view diagram illustrating a conventional die package undergoing an unbiased highly accelerated stress test (uHAST). Under the high temperature and high humidity test condition, the cracks can further increase, which can ultimately cause pads 203 to be exposed, and become susceptible to corrosion, resulting in chip failures.

[0048] FIG. 7 is a cross-section view diagram illustrating a curing process of a die package according to an embodiment of the present invention. As shown in FIG. 7, part of organic polymer 501 is extended into trenches 301. As a result, the contact area between the organic polymer and the die is increased, leading to enhanced adhesion and better stress distribution. Under this condition, the stress on the second passivation layer caused by the shrinkage or contraction of the organic polymer can be reduced or avoided. It is less likely that pads 203 are exposed to cause corrosion and failure. The reliability and yield of the package can be improved.

[0049] According to some embodiments, the present invention also provides a package as illustrated in FIG. 5. As shown in FIG. 5, the package includes a die, which includes a substrate 201 having a circuit, a first passivation layer 202 on the substrate, a plurality of pads 203 on the first passivation layer, and a second passivation layer 204 disposed on the first passivation layer and covering the plurality of pads. The package also includes one or more trenches 301 in a portion of the second passivation layer that overlies a portion of the first passivation layer on the outside of the plurality of pads. The package also includes an organic polymer overlying the die and filling the trenches. A portion of the second passivation layer overlying the pads protrudes above the other portion of the second passivation layer not covering pads. In some embodiments, the first passivation layer 202 may include a stack of one or more nitride layers 212 and one or more oxide layers 222, and the second passivation layer 204 may include one or more nitride layers 224 and one or more oxide layers 214.

[0050] In some embodiments, trenches 301 can extend into the first passivation layer 202. In some embodiments, the first passivation layer 202 may include a first dielectric layer, a second dielectric layer stack, and a third dielectric layer. In this case, trenches 301 can stop at the first, second, or third dielectric layer. In a particular embodiment, the second passivation layer stops at the second dielectric layer.

[0051] In one embodiment, as shown in FIG. 3A, the plurality of pads may include a pad 203 adjacent to a first edge of the substrate or die. In other words, pad 203 is the outermost pad of the plurality of pads. Trench 301 is formed in the second passivation layer closest to the outer edge of the substrate. As described above, the edge region of the pad array is susceptible to stress buildup, because of the rising step of the second passivation layer over the pads. In addition, one or more trenches 301 may be annular grooves. In some embodiments, there are two or more annular trenches or grooves. In one embodiment, the package may also include sealing structures, e. g., a seal ring 205 in the vicinity of the die edge around the circuit, and trenches 301 can be located between the pads 203 and the seal structure 205.

[0052] Thus, a device package structure and a manufacturing method have been described in detail. While the present invention is described herein with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Rather, the purpose of the illustrative embodiments is to make the spirit of the present invention be better understood by those skilled in the art. In order not to obscure the scope of the invention, many details of well-known processes and manufacturing techniques are omitted. Various modifications of the illustrative embodiments as well as other embodiments will be apparent to those of skill in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications. Furthermore, some of the features of the preferred embodiments of the present invention could be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles of the invention, and not in limitation thereof.