Backplane bus structure of communication system and board recognition method using same

Abstract

The present invention relates to the prevention of bus conflicts in the backplane by providing a bus structure which is configured to control the activation of an attached slave board in the backplane to/from which a plurality of slave boards are attached and detached. The backplane according to the present invention can prevent data bus conflicts and improve the stability of a corresponding system by configuring general purpose I/O (GPIO) pins in a 2 bit request/grant scheme between a master board and the plurality of slave boards. Accordingly, the present invention can improve system reliability, maintainability, and competitiveness in various fields such as the fields of communication devices and server devices, remote monitors and control systems, vessel communications, aircraft communications, and wired and wireless communications in which various protocols are combined and implemented.

Claims

1. A board recognition method using a backplane bus structure of a communication system comprising (a) first and second master boards configured to perform data communication based on a set communication protocol; (b) a backplane configured to support at least one communication bus; (c) a slave board detachably connected to the backplane and configured to perform data communication with each master board; and (d) a General Purpose I/O pins (GPIO) bus configured on the backplane to connect the first master board to the at least one slave board, the General Purpose I/O pins (GPIO) bus being to enable communication of a request and an approval regarding whether to activate data communication between the first master board or the second master board and the slave board, the method comprising: a) determining, by the first master board, whether the slave board has been mounted on the backplane by checking whether a mounting check signal has been received by the first master board via the General Purpose I/O pins (GPIO) bus; b) determining, by the first master board, whether the first master board or the second master board performs data communication if it is determined that the slave board has been mounted; c) activating, by the first master board, the slave board through the General Purpose I/O pins (GPIO) bus to turn on a data communication line if it is determined that the second master board does not perform data communication; and d) performing, by the first master board, data communication via the data communication line with the slave board mounted on the backplane, based on the set communication protocol if the slave board has been activated to turn on the data communication line, wherein, the step of determining whether the second master board performs data communication further comprises the steps of: i) transmitting, by the first master board, a heart bit to the second master board; ii) receiving, by the first master board, a response signal in response to the transmission of the heart bit; iii) checking the response signal by the first master board, and determining whether the second master board performs data communication; and iv) determining by the first master board that the slave board can be activated if the second master board does not perform data communication.

2. The board recognition method of claim 1, wherein the step of determining whether the slave board has been mounted on the backplane further comprises the steps of: i) checking, by the first master board, whether the mounting check signal has been received through the GPIO bus by the first master board; ii) identifying, by the first master board, a slot through which the corresponding mounting check signal has been received if the mounting check signal has been received; and iii) determining, by the first master board, that the slave board has been mounted in the slot.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram showing an embodiment of a backplane bus structure of a communication system according to the present invention;

(2) FIG. 2 is a flowchart showing an embodiment of a board recognition method using the backplane bus structure of FIG. 1;

(3) FIG. 3 is a flowchart showing a detailed embodiment of step S110 of FIG. 2;

(4) FIG. 4 is a flowchart showing a detailed embodiment of step S120 of FIG. 2;

(5) FIG. 5 is a block diagram showing another embodiment of a backplane bus structure of a communication system according to the present invention;

(6) FIG. 6 is a flowchart showing an embodiment of a board recognition method using the backplane bus structure of FIG. 5;

(7) FIG. 7 is a flowchart showing a detailed embodiment of step S210 of FIG. 6;

(8) FIG. 8 is a flowchart showing a detailed embodiment of step S220 of FIG. 6; and

(9) FIG. 9 is a flowchart showing a detailed embodiment of step S230 of FIG. 6.

DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS

(10) Embodiments of a backplane bus structure of a communication system and a board recognition method using the backplane bus structure according to the present invention may be applied in various manners. Hereinafter, preferred embodiments of the invention will be described in detail with reference to the attached drawings.

(11) FIG. 1 is a block diagram showing an embodiment of a backplane bus structure of a communication system according to the present invention.

(12) Referring to FIG. 1, the backplane bus structure of a communication system includes a “Master Central Processing Unit: MCPU Board” that is a master board, a backplane, slave boards, and a General Purpose I/O pins (GPIO) bus.

(13) The master board performs data communication (hereinafter also referred to as “data transmission”) with the slave boards via the backplane based on set communication protocols. In an embodiment, the master board may provide slot identifiers (slot IDs) to perform data communication with the slave boards. It is apparent that, since the configuration of the master board and the type and number of communication protocols processed by the master board may be modified in various forms depending on the requirements of those skilled in the art, they are not limited to specific examples.

(14) The backplane enables the master board and a plurality of slave boards to smoothly perform data communication by supporting at least one communication bus. In an embodiment, terminators are configured at both ends of the communication bus, so that, when traffic increases, redundant signals are absorbed to stably maintain a data transfer speed on the backplane.

(15) The slave boards are detachably connected to the backplane to perform data communication with the master board. In an embodiment, each slave board may be provided with a “slot ID” to perform data communication with the master board. Further, each slave board may be configured to support a “hot swap” function. Here, “hot swap” denotes a function of repairing or replacing specific parts even in a state in which the system is supplied with and operated by power.

(16) The GPIO bus is configured on the backplane to connect the master board to at least one slave board and is used to make a request and an approval regarding whether to activate data communication between the master board and the at least one slave board.

(17) In an embodiment, the GPIO bus may be used so that at least one slave board requests the master board to activate at least one communication bus (bus corresponding to a communication protocol used in the corresponding slave board), and the master board responds to the activation request.

(18) A method of recognizing a slave board using such a GPIO bus will be described in detail later.

(19) Further, a physical transmission scheme for data communication based on the communication bus configured on the backplane may be implemented to more robustly perform data communication using a “differential line drive/receiver” scheme or a “Low Voltage Differential Signal (LVDS)” scheme.

(20) FIG. 2 is a flowchart showing an embodiment of a board recognition method using the backplane bus structure of FIG. 1, FIG. 3 is a flowchart showing a detailed embodiment of step S110 of FIG. 2, and FIG. 4 is a flowchart showing a detailed embodiment of step S120 of FIG. 2.

(21) Referring to FIG. 2, the master board determines whether a detachably configured board has been mounted on the backplane by checking whether a mounting check signal to be transmitted has been received through a GPIO bus (step S110).

(22) More specifically, as shown in FIG. 3, the master board may check whether a mounting check signal has been received through the GPIO bus (step S112), in order to continuously determine whether a slave board has been mounted in a state in which the system is operated (step S111). In an embodiment, the mounting check signal may include a data communication request signal. For example, the data communication request signal may include a 1-bit signal input through the GPIO bus.

(23) If the mounting check signal has been received through the GPIO bus (step S113), the master board may identify a slot through which the corresponding mounting check signal is received (step S114). In an embodiment, the identification of the slot in which the slave board is mounted may be performed by verifying the slot identifier (ID) of the slot. For example, the slot ID may be transmitted together with the mounting check signal to the master board through the GPIO bus.

(24) If the mounting check signal is received from the specific slot, the master board may determine that the corresponding board (slave board) has been mounted in the slot.

(25) If it is determined that the corresponding board has been mounted, the master board activates the board through the GPIO bus (step S120).

(26) This procedure is described in detail below. As shown in FIG. 4, if it is determined that the corresponding board has been mounted in the slot (step S121), the master board may determine whether the board is operable (step S122). For example, the determination of whether the corresponding board is operable may be performed by checking whether the system uses a supportable communication protocol, whether the board has been normally connected, or whether power has been supplied to the corresponding board (in the case of a repair of the board, power is cut off).

(27) If it is determined that the corresponding board is normally operable (step S123), the master board may activate the board through the GPIO bus (step S124). For example, the activation of the board may be performed by the master board transmitting a 1-bit signal to the board through the GPIO bus.

(28) In an embodiment, when the mounting check signal is received, the master board may activate the corresponding board by transmitting a response signal (data communication approval signal) to the received mounting check signal (data communication request signal) to the board.

(29) Once the board is activated by the master board, the board may turn on a data communication line. When the data communication line is turned on in this way, the master board performs data communication with the board mounted on the backplane, based on a set communication protocol (step S130).

(30) Below, in the description of another embodiment of a backplane bus structure of a communication system according to the present invention, a dual system in which two master boards are configured will be described as an example. Of course, it is apparent that the present invention is not limited to the dual system corresponding to another embodiment, which will be described below, and the present invention may be applied to a parallel processing system or the like including at least two master boards at the request of those skilled in the art.

(31) FIG. 5 is a block diagram showing another embodiment of a backplane bus structure of a communication system according to the present invention.

(32) Referring to FIG. 5, the backplane bus structure of a communication system includes at least two master boards configured to perform data communication based on set communication protocols; a backplane configured to support at least one communication bus; at least one slave board detachably connected to the backplane to perform data communication with each master board; and a General Purpose I/O pins (GPIO) bus configured on the backplane to connect a first one of the at least two master boards to the at least one slave board, and used to make a request and an approval regarding whether to activate data communication between the corresponding master board and the slave board.

(33) In an embodiment, the backplane further includes a heart bit bus that is configured to connect the at least two master boards, thus allowing the first one of the at least two master boards to determine whether a second master board performs data communication.

(34) Further, the backplane may be configured to perform a switching operation depending on whether the corresponding master board performs data communication, which can be determined through the heart bit bus, upon configuring communication buses that connect each master board to slave boards.

(35) The GPIO bus may be used such that, if a first master board determines, through the heart bit bus, that a second master board does not perform data communication, the at least one slave board requests the first master board to activate at least one communication bus, and the first master board responds to the activation request.

(36) FIG. 6 is a flowchart showing an embodiment of a board recognition method using the backplane bus structure of FIG. 5, FIG. 7 is a flowchart showing a detailed embodiment of step S210 of FIG. 6, FIG. 8 is a flowchart showing a detailed embodiment of step S220 of FIG. 6, and FIG. 9 is a flowchart showing a detailed embodiment of step S230 of FIG. 6.

(37) Referring to FIG. 6, a first one of at least two master boards determines whether a slave board has been mounted on the backplane by checking whether a mounting check signal to be transmitted has been received through a GPIO bus (step S210).

(38) This is described in detail below. As shown in FIG. 7, in order to continuously determine whether a slave board has been mounted during the operation of the system (step S211), the first master board may check whether a mounting check signal has been received through the GPIO bus (step S212). For example, a data communication request signal may include a 1-bit signal input through the GPIO bus.

(39) If the mounting check signal has been received through the GPIO bus (step S213), the first master board may identify a slot through which the corresponding mounting check signal is received (step S214). In an embodiment, the identification of the slot in which the slave board is mounted may be performed by verifying the slot ID of the slot. For example, the slot ID may be transmitted together with the mounting check signal to the first master board through the GPIO bus.

(40) When the mounting check signal is received from a specific slot, the first master board may determine that the slave board has been mounted in the slot.

(41) As a result of the determination, if the slave board has been mounted, the first master board determines whether a second one of the at least two master boards performs data communication (step S220).

(42) This procedure is described below. As shown in FIG. 8, if the first master board has determined the mounting of the slave board (step S221), it may transmit a heart bit to the second master board (step S222) and may receive a response signal to the result of the transmission from the second master board (step S223).

(43) The first master board may determine whether the second master board performs data communication by checking the response signal received from the second master board (step S224).

(44) In this case, if it is determined that the second master board does not perform data communication (step S225), the first master board may determine that the corresponding slave board can be activated (step S226).

(45) If the second master board performs data communication (step S225), the first master board may determine that the corresponding slave board cannot be activated (step S227).

(46) Therefore, at steps S225 to S227 of FIG. 8, the first master board may activate the corresponding slave board while preventing a collision caused by the use of the communication bus.

(47) If it is determined that the second master board does not perform data communication, the first master board activates the corresponding slave board through the GPIO bus (step S230).

(48) This procedure is described in detail. As shown in FIG. 9, if it is determined that the slave board can be activated (step S231), the first master board may determine whether the slave board is operable (step S232).

(49) If it is determined that the slave board is normally operable (step S233), the first master board may activate the corresponding slave board through the GPIO bus (step S234). For example, the activation of the slave board may be performed by the first master board transmitting a 1-bit signal to the slave board through the GPIO bus.

(50) When the slave board is activated by the first master board, the slave board may turn on a data communication line. Once the data communication line is turned on in this way, the first master board performs data communication with the slave board mounted on the backplane, based on a set communication protocol (step S240).

(51) As described above, the backplane bus structure of the communication system and the board recognition method using the backplane bus structure according to the present invention have been described. Those skilled in the art to which the present invention pertains will understand that the technical configuration of the present invention may be practiced in other detailed forms without departing from the technical spirit or essential features of the invention.

(52) Therefore, the above-described embodiments of the present invention should be understood to be exemplary in all aspects, rather than restrictive. The scope of the present invention is defined by the accompanying claims rather than the above detailed descriptions, and then all changes or modifications derived from the meanings and scope of the claims and equivalents thereof should be interpreted as being included in the scope of the present invention.

(53) The present invention may improve the reliability, maintainability and product competitiveness of systems in various fields, such as communication equipment and server equipment, remote monitoring and control systems, vessel communication, aeronautical communication, and wired/wireless communication for integrating and operating various communication protocols.