Semiconductor device and driving method thereof

Abstract

An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.

Claims

1. A semiconductor device comprising: a configuration memory comprising a static random access memory, and a cyclic redundancy check memory comprising a plurality of memory elements being in a matrix, each memory element including: a first transistor; a second transistor; a capacitor; and a data storage portion configured to store data for an error detection, wherein the data storage portion includes one of a source and a drain of the first transistor, a gate of the second transistor, and a first electrode of the capacitor, wherein the first transistor comprises an oxide semiconductor layer, wherein the cyclic redundancy check memory is less susceptible to soft errors than the configuration memory, and wherein the cyclic redundancy check memory is stacked over the configuration memory.

2. The semiconductor device according to claim 1, wherein the error detection is a cyclic redundancy check, and wherein the data for the error detection is a remainder used for the cyclic redundancy check.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer in the first transistor has a thickness of 20 nm or less.

4. The semiconductor device according to claim 1, further comprising a third transistor, wherein one of a source and a drain of the second transistor is connected to one of a source and a drain of the third transistor.

5. The semiconductor device according to claim 4, further comprising a fourth transistor, wherein a second electrode of the capacitor is connected to one of a source and a drain of the fourth transistor.

6. The semiconductor device according to claim 1, further comprising a third transistor, wherein the data storage portion further includes a gate of the third transistor.

7. The semiconductor device according to claim 1, wherein the capacitor has a capacitance of 1 fF or more.

8. A semiconductor device comprising: a first memory comprising a static random access memory, and a second memory comprising a plurality of memory elements being in a matrix, each memory element including: a first transistor; a second transistor; a capacitor; and a data storage portion configured to store data for an error detection, wherein the data storage portion includes one of a source and a drain of the first transistor, a gate of the second transistor, and a first electrode of the capacitor, wherein the first transistor comprises an oxide semiconductor layer, wherein the second memory is less susceptible to soft errors than the first memory, and wherein the second memory is stacked over the first memory.

9. The semiconductor device according to claim 8, wherein the error detection is a cyclic redundancy check, and wherein the data for the error detection is a remainder used for the cyclic redundancy check.

10. The semiconductor device according to claim 8, wherein the oxide semiconductor layer in the first transistor has a thickness of 20 nm or less.

11. The semiconductor device according to claim 8, further comprising a third transistor, wherein one of a source and a drain of the second transistor is connected to one of a source and a drain of the third transistor.

12. The semiconductor device according to claim 11, further comprising a fourth transistor, wherein a second electrode of the capacitor is connected to one of a source and a drain of the fourth transistor.

13. The semiconductor device according to claim 8, further comprising a third transistor, wherein the data storage portion further includes a gate of the third transistor.

14. The semiconductor device according to claim 8, wherein the capacitor has a capacitance of 1 fF or more.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the accompanying drawings:

(2) FIGS. 1A and 1B each illustrate a memory element of a semiconductor device which is one embodiment of the present invention;

(3) FIG. 2 illustrates a memory element of a semiconductor device which is one embodiment of the present invention;

(4) FIGS. 3A and 3B each illustrate a memory element of a semiconductor device which is one embodiment of the present invention;

(5) FIGS. 4A to 4C illustrate a configuration memory and a CRC memory of a semiconductor device which is one embodiment of the present invention;

(6) FIG. 5 is a first diagram illustrating a method for driving a semiconductor device which is one embodiment of the present invention; and

(7) FIG. 6 is a second diagram illustrating a method for driving a semiconductor device which is one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(8) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Accordingly, the present invention should not be construed as being limited to the description of the embodiments below.

(9) First, description is made on a configuration of a memory element which can be used for a semiconductor device of one embodiment of the present invention, and the operation thereof. Then, description is made on a CRC which can be used in a method for driving a semiconductor device of one embodiment of the present invention.

Embodiment 1

(10) A configuration of a memory element which can be used for a semiconductor device of one embodiment of the present invention, and the operation thereof will be described.

(11) Note that the description in this embodiment is made focusing on one memory element; however, in an actual semiconductor device, a plurality of memory elements are arranged in a matrix.

(12) FIG. 1A illustrates an example of the configuration of the memory element that can be used for the semiconductor device of one embodiment of the present invention. A memory element 100 illustrated in FIG. 1A includes a first transistor 102, a second transistor 104, a capacitor 106, and a data storage portion 118, and is electrically connected to a first terminal 108, a second terminal 110, a third terminal 112, a fourth terminal 114, and a fifth terminal 116.

(13) One of a source and a drain of the first transistor 102 is electrically connected to the third terminal 112. The other of the source and the drain of the first transistor 102 is electrically connected to a first electrode of the capacitor 106 and a gate of the second transistor 104. A gate of the first transistor 102 is electrically connected to the first terminal 108.

(14) One of a source and a drain of the second transistor 104 is electrically connected to the fourth terminal 114. The other of the source and the drain of the second transistor 104 is electrically connected to the fifth terminal 116.

(15) A second electrode of the capacitor 106 is electrically connected to the second terminal 110. Note that the capacitor 106 preferably has a capacitance of 1 fF (femto farad) or more.

(16) The data storage portion 118 is formed in an area in which the other of the source and the drain of the first transistor 102, the first electrode of the capacitor 106, and the gate of the second transistor 104 are electrically connected to each other.

(17) Any transistor having low off-state current can be used as the first transistor 102. A channel formation region of the first transistor 102 is preferably a thin semiconductor layer, and more preferably a semiconductor layer with a thickness of 20 nm or less. By using such a thin semiconductor layer for the channel formation region, the amount of charge generated by a nuclear reaction by irradiation with high energy neutrons can be reduced to about 1/10 or less of that in a bulk semiconductor. The use of a large band gap material for the semiconductor layer including a channel allows a further reduction in the amount of charge generated. An example of such a large band gap material is an oxide semiconductor.

(18) For example, in a semiconductor with a band gap of 3.2 eV (e.g., an oxide semiconductor), the amount of charge generated per unit length in an area through which a particles produced by the nuclear reaction pass is about ⅓ of that in a semiconductor with a band gap of 1.1 eV (e.g., silicon). It is generally said that a charge of several hundreds of femto coulombs (fC) is generated in a nuclear reaction in silicon. In a semiconductor with a band gap of 3.2 eV and a thickness of 20 nm, the amount of charge generated is less than 1 fC.

(19) Thus, when a semiconductor layer serving as the channel formation region of the first transistor 102 is formed thin using a large band gap material, the first transistor 102 has sufficient stability against a nuclear reaction occurring due to irradiation with high energy neutrons, whereby the data storage portion 118 has high storage capability.

(20) Note that the semiconductor layer serving as the channel formation region of the first transistor 102 preferably has no PN junction, and the single semiconductor layer preferably includes a single transistor (channel). This is because in the case where the semiconductor layer has PN junction and channels of a plurality of transistors are provided in the semiconductor layer (that is, the single semiconductor layer includes a plurality of transistors), all the transistors in the semiconductor layer might be affected by a nuclear reaction due to parasitic bipolar effect.

(21) Any transistor having a switching function can be used as the second transistor 104. For example, the second transistor 104 may be a transistor in which a channel is formed in a silicon substrate. The second transistor 104 may be either a p-channel transistor or an n-channel transistor.

(22) A signal is input to the first terminal 108 and the third terminal 112 at least when data is written to the data storage portion 118. Data for detecting an error is input to the third terminal 112. A memory subjected to error detection is, for example, the one included in a configuration memory 400 illustrated in FIGS. 4A and 4B. A signal is input to the second terminal 110 at least when data is read out from the data storage portion 118. A signal is output from the fifth terminal 116 at least when data is read out from the data storage portion 118. Note that the timing of inputting and outputting signals to and from the first terminal 108, the second terminal 110, the third terminal 112, the fourth terminal 114, and the fifth terminal 116 is not limited to the above.

(23) Next, operation of the memory element 100 illustrated in FIG. 1A will be described. When data is written to the memory element 100, the potential of the first terminal 108 is controlled so that the first transistor 102 is turned on, and the third terminal 112 is controlled to have a potential of data to be written. In the case where the first transistor 102 is an n-channel transistor as illustrated in FIG. 1A, it is turned on when the first terminal 108 has a high potential; in the case where the first transistor 102 is a p-channel transistor, it is turned on when the first terminal 108 has a low potential.

(24) By controlling the potentials in the above manner, the potential of the data storage portion 118 becomes a potential corresponding to the potential of the third terminal 112, preferably, a potential equal to the potential of the third terminal 112. That is, data is written to the data storage portion 118. After the data is written to the data storage portion 118, the potential of the first terminal 108 is controlled so that the first transistor 102 is turned off, whereby the data is stored in the data storage portion 118. Since a transistor with a low off-state current is used as the first transistor 102, the potential of the data storage portion 118 is kept for a sufficient time (10 ms or more). If the data is stored in the data storage portion 118 for a longer time, refresh operation may be performed.

(25) When data is read out from the memory element 100, the potential of the second terminal 110 is set to a potential to be read out, and the data of the data storage portion 118 is determined with the on-resistance of the second transistor 104.

(26) For example, in the case where the second transistor 104 is an n-channel transistor, the second transistor 104 has a low on-resistance when the data storage portion 118 has a high potential, so that a signal input to the fourth terminal 114 is transmitted to the fifth terminal 116. On the other hand, the second transistor 104 has a high on-resistance when the data storage portion 118 has a low potential; therefore, a signal input to the fourth terminal 114 is not transmitted to the fifth terminal 116.

(27) In the case where the second transistor 104 is a p-channel transistor, the second transistor 104 has a high on-resistance when the data storage portion 118 has a high potential, and thus a signal input to the fourth terminal 114 is not transmitted to the fifth terminal 116. On the other hand, the second transistor 104 has a low on-resistance when the data storage portion 118 has a low potential, so that a signal input to the fourth terminal 114 is transmitted to the fifth terminal 116.

(28) Note that the potential of the third terminal 112 is preferably higher than or equal to the highest potential value of the data storage portion 118 or lower than or equal to the lowest potential value of the data storage portion 118. For example, the high potential of the data storage portion 118 is +1 V and the low potential thereof is 0 V.

(29) FIG. 1B illustrates an example of the configuration of the memory element that can be used for the semiconductor device of one embodiment of the present invention, which is different from that of FIG. 1A. A memory element 150 illustrated in FIG. 1B includes a first transistor 152, a second transistor 154, a third transistor 156, a capacitor 158, and a data storage portion 172, and is electrically connected to a first terminal 160, a second terminal 162, a third terminal 164, a fourth terminal 166, a fifth terminal 168, and a sixth terminal 170.

(30) The first transistor 152 has a structure similar to that of the first transistor 102 in FIG. 1A. The second transistor 154 and the third transistor 156 have a structure similar to that of the second transistor 104 in FIG. 1A. The data storage portion 172 is formed in an area in which one of a source and a drain of the first transistor 152, a first electrode of the capacitor 158, and a gate of the second transistor 154 are electrically connected to each other.

(31) A signal is input to the first terminal 160 and the third terminal 164 at least when data is written to the data storage portion 172. Data for detecting an error is input to the third terminal 164. A memory subjected to error detection is, for example, the one included in the configuration memory 400 illustrated in FIGS. 4A and 4B. A signal is input to the second terminal 162 at least when data is read out from the data storage portion 172. A signal is output from the sixth terminal 170 at least when data is read out from the data storage portion 172. Note that the timing of inputting and outputting signals to and from the first terminal 160, the second terminal 162, the third terminal 164, the fourth terminal 166, the fifth terminal 168, and the sixth terminal 170 is not limited to the above.

(32) Next, operation of the memory element 150 illustrated in FIG. 1B will be described. Data is written to the memory element 150 in a manner similar to that in the case where data is written to the memory element 100 in FIG. 1A; thus, the above description is referred to and description is omitted here.

(33) When data is read out from the memory element 150, the potential of the second terminal 162 is controlled so that the third transistor 156 is turned on. Data of the data storage portion 172 can be determined because the on-resistance of the second transistor 154 changes with the potential of the data storage portion 172.

(34) In the memory element 150 in FIG. 1B, the control of the potential of the fifth terminal 168 allows the potential of the data storage portion 172 to be largely varied.

(35) For example, description is made on the case where the second transistor 154 is an re-channel transistor and the capacitance of the capacitor 158 is equal to the capacitance (gate capacitance) of the second transistor 154 which is on. The potential of the third terminal 164 is set to +1 V and the potential of the fifth terminal 168 is set to 0 V, whereby data having a high potential is written to the data storage portion 172. In a period during which the data of the data storage portion 172 is kept, the fifth terminal 168 is set to +1 V. Then, the data storage portion 172 has a potential of +1.5 V. Note that the potential of the fourth terminal 166 is set to +2.0 V.

(36) In the case where the second transistor 154 is a p-channel transistor and the capacitance of the capacitor 158 is equal to the capacitance of the second transistor 154 which is on, the data storage portion 172 has a potential of +2 V when data having a high potential is written to the data storage portion 172 in the above manner.

Embodiment 2

(37) FIG. 2 illustrates an example of the configuration of the memory element that can be used for the semiconductor device of one embodiment of the present invention, which is different from those of FIGS. 1A and 1B. A memory element 200 illustrated in FIG. 2 includes a first transistor 202, a second transistor 204, a third transistor 206, a fourth transistor 208, a capacitor 210, and a data storage portion 226, and is electrically connected to a first terminal 212, a second terminal 214, a third terminal 216, a fourth terminal 218, a fifth terminal 220, a sixth terminal 222, and a seventh terminal 224.

(38) The first transistor 202 has a structure similar to that of the first transistor 102 in FIG. 1A. The fourth transistor 208 has a structure similar to that of the first transistor 102 or the second transistor 104 in FIG. 1A. The second transistor 204 and the third transistor 206 have a structure similar to that of the second transistor 104 in FIG. 1A. The data storage portion 226 is formed in an area in which one of a source and a drain of the first transistor 202, a first electrode of the capacitor 210, and a gate of the second transistor 204 are electrically connected to each other.

(39) A signal is input to the first terminal 212, the third terminal 216, and the fourth terminal 218 at least when data is written to the data storage portion 226. Data for detecting an error is input to the fourth terminal 218. A memory subjected to error detection is, for example, the one included in the configuration memory 400 illustrated in FIGS. 4A and 4B. A signal is input to the second terminal 214 at least when data is read out from the data storage portion 226. A signal is output from the seventh terminal 224 at least when data is read out from the data storage portion 226. Note that the timing of inputting and outputting signals to and from the first terminal 212, the second terminal 214, the third terminal 216, the fourth terminal 218, the fifth terminal 220, the sixth terminal 222, and the seventh terminal 224 is not limited to the above.

(40) The memory element 200 illustrated in FIG. 2 includes the fourth transistor 208. When data is written to an arbitrary row and other rows, the fourth transistor 208 is synchronized with the first transistor 202, in other words, the fourth transistor 208 and the first transistor 202 are turned on/off at the same timing, which prevents a decrease in the potential of the data storage portion 226 in a period during which data is written to the other rows. For example, the fourth transistor 208 and the first transistor 202 are turned off when data is written to the other rows.

(41) After the data writing is completed, the fourth transistor 208 is turned on while the first transistor 202 is kept off, and the potential of the sixth terminal 222 is set to an appropriate value. Thus, as in the memory element in FIG. 1B, the potential of the data storage portion 226 can be changed.

(42) Note that the other configuration of the memory element 200 in FIG. 2 is similar to those of the memory element 100 in FIG. 1A and the memory element 150 in FIG. 1B; thus, the description in Embodiment 1 is referred to and description is omitted here.

Embodiment 3

(43) In the memory element 100 and the memory element 150 described in Embodiment 1 and the memory element 200 described in Embodiment 2, it is necessary to make a potential difference between at least two terminals (precharge operation) before data is read out. For example, in the memory element 100 in FIG. 1A, the fourth terminal 114 and the fifth terminal 116 need to have potentials different from each other.

(44) Next, description is made on an example of the configuration of the memory element that can be used for the semiconductor device of one embodiment of the present invention, in which precharge operation is unnecessary (see FIGS. 3A and 3B).

(45) FIG. 3A illustrates an example of the configuration of the memory element that can be used for the semiconductor device of one embodiment of the present invention, in which precharge operation is unnecessary. A memory element 300 illustrated in FIG. 3A includes a first transistor 302, a second transistor 304, a third transistor 306, a fourth transistor 308, a capacitor 310, and a data storage portion 326, and is electrically connected to a first terminal 312, a second terminal 314, a third terminal 316, a fourth terminal 318, a fifth terminal 320, a sixth terminal 322, and a seventh terminal 324.

(46) The first transistor 302 has a structure similar to that of the first transistor 102 in FIG. 1A. The second transistor 304, the third transistor 306, and the fourth transistor 308 have a structure similar to that of the second transistor 104 in FIG. 1A. Note that the second transistor 304 and the third transistor 306 have different conductivity types as described later. The data storage portion 326 is formed in an area in which one of a source and a drain of the first transistor 302, a first electrode of the capacitor 310, a gate of the second transistor 304, and a gate of the third transistor 306 are electrically connected to each other.

(47) A signal is input to the first terminal 312 and the third terminal 316 at least when data is written to the data storage portion 326. Data for detecting an error is input to the third terminal 316. A memory subjected to error detection is, for example, the one included in the configuration memory 400 illustrated in FIGS. 4A and 4B. A signal is input to the second terminal 314 at least when data is read out from the data storage portion 326. A signal is output from the seventh terminal 324 at least when data is read out from the data storage portion 326. Note that the timing of inputting and outputting signals to and from the first terminal 312, the second terminal 314, the third terminal 316, the fifth terminal 320, and the seventh terminal 324 is not limited to the above.

(48) Note that the fourth terminal 318 is electrically connected to a high potential power source line Vdd and the sixth terminal 322 is electrically connected to a low potential power source line Vss. Alternatively, the fourth terminal 318 and the sixth terminal 322 may be electrically connected to the low potential power source line Vss and the high potential power source line Vdd, respectively.

(49) In the memory element 300 illustrated in FIG. 3A, an inverter is configured by the second transistor 304 and the third transistor 306. An input of the inverter is electrically connected to the data storage portion 326 and an output of the inverter is electrically connected to one of a source and a drain of the fourth transistor 308. Note that the other of the source and the drain of the fourth transistor 308 is electrically connected to the seventh terminal 324 which corresponds to the fifth terminal 116 in FIG. 1A.

(50) It can also be said that the memory element 300 illustrated in FIG. 3A has the configuration in which the second transistor 304 and the terminal 318 electrically connected to the power source line are added to the memory element 150 illustrated in FIG. 1B.

(51) In the memory element 300 illustrated in FIG. 3A, the potential of the high potential power source line Vdd or the low potential power source line Vss can be output from the seventh terminal 324 without precharge operation, resulting in an increase in reading speed.

(52) Instead of the configuration illustrated in FIG. 3A, a configuration illustrated in FIG. 3B may be employed. FIG. 3B illustrates an example of the configuration of the memory element that can be used for the semiconductor device of one embodiment of the present invention, in which precharge operation is unnecessary. A memory element 350 illustrated in FIG. 3B includes a first transistor 352, a second transistor 354, a third transistor 356, a fourth transistor 358, a fifth transistor 360, a capacitor 362, and a data storage portion 380, and is electrically connected to a first terminal 364, a second terminal 366, a third terminal 368, a fourth terminal 370, a fifth terminal 372, a sixth terminal 374, a seventh terminal 376, and an eighth terminal 378.

(53) The first transistor 352 and the fifth transistor 360 have a structure similar to that of the first transistor 102 in FIG. 1A. The second transistor 354, the third transistor 356, and the fourth transistor 358 have a structure similar to that of the second transistor 104 in FIG. 1A. Note that the second transistor 354 and the third transistor 356 have different conductivity types as those in FIG. 3A. The data storage portion 380 is formed in an area in which one of a source and a drain of the first transistor 352, a first electrode of the capacitor 362, a gate of the second transistor 354, and a gate of the third transistor 356 are electrically connected to each other.

(54) A signal is input to the first terminal 364, the second terminal 366, and the fourth terminal 370 at least when data is written to the data storage portion 380. Data for detecting an error is input to the fourth terminal 370. A memory subjected to error detection is, for example, the one included in the configuration memory 400 illustrated in FIGS. 4A and 4B. A signal is input to the third terminal 368 at least when data is read out from the data storage portion 380. A signal is output from the eighth terminal 378 at least when data is read out from the data storage portion 380. Note that the timing of inputting and outputting signals to and from the first terminal 364, the second terminal 366, the third terminal 368, the fourth terminal 370, and the eighth terminal 378 is not limited to the above.

(55) Note that the fifth terminal 372 is electrically connected to the high potential power source line Vdd and the seventh terminal 376 is electrically connected to the low potential power source line Vss. Alternatively, the fifth terminal 372 and the seventh terminal 376 may be electrically connected to the low potential power source line Vss and the high potential power source line Vdd, respectively.

(56) It can also be said that the memory element 350 illustrated in FIG. 3B has the configuration in which the second transistor 354 and the terminal electrically connected to the power source line are added to the memory element 200 illustrated in FIG. 2.

(57) As described above in Embodiments 1 to 3, there is a variety of examples of configurations of the memory element that can be used for the semiconductor device of one embodiment of the present invention.

(58) In the configurations illustrated in FIGS. 1A and 1B, the second terminal 110 and the fifth terminal 168 control the potentials of the data storage portion 118 and the data storage portion 172 to be largely varied. The same applies to the sixth terminal 222 in FIG. 2, the fifth terminal 320 in FIG. 3A, and the sixth terminal 374 in FIG. 3B.

(59) In the configuration illustrated in FIG. 2, a decrease in the potential of the data storage portion 226 can be prevented by the fourth transistor 208 and the third terminal 216 in a period during which data is written to the other rows, as compared to the configurations illustrated in FIGS. 1A and 1B. The same applies to FIG. 3B.

(60) In the configurations illustrated in FIGS. 3A and 3B, unlike in the configurations illustrated in FIGS. 1A and 1B and FIG. 2, precharge operation is unnecessary.

(61) The memory element that can be used for the semiconductor device of one embodiment of the present invention can be obtained in the aforementioned manner. Note that the memory element that can be used for the semiconductor device of one embodiment of the present invention is not limited to the above examples, and may be modified in a variety of ways without departing from the spirit of the invention.

(62) Note that in one embodiment of the present invention, the aforementioned memory elements only need to be employed for part of the semiconductor device.

Embodiment 4

(63) Next, description is made on a method for driving a semiconductor device of one embodiment of the present invention, in which a CRC is performed. FIG. 4A illustrates the configuration memory 400 and a CRC memory 402 which are used in the driving method of a semiconductor device of one embodiment of the present invention. According to FIG. 4A, each row of the configuration memory is provided with a corresponding CRC memory. The CRC memory 402 has a capacitance equivalent to the number of rows multiplied by the number of bits of the CRC. That is, FIG. 4A shows an 8-bit CRC, and thus the CRC memory needs a capacitance equivalent to 256×8=2048 bits. Note that the number of bits of the CRC is not limited to 8.

(64) The configuration memory 400 may include an SRAM or the like, or any of the memory elements described with reference to FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B.

(65) The CRC memory 402 includes any of the memory elements described with reference to FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B.

(66) Note that the configuration memory 400 and the CRC memory 402 may be separated by physical distance or provided close to each other. Alternatively, the CRC memory 402 may be stacked over the configuration memory 400.

(67) FIG. 4B illustrates other circuits and the like which are used for the CRC in addition to the configuration memory 400 and the CRC memory 402. Data is written to and read from the configuration memory 400 and the CRC memory 402 by a data input/output circuit 404. The data input/output circuit 404 allows data to be transmitted to and received from a CRC arithmetic circuit 406 and a boot memory 408.

(68) Data to be written to the configuration memory 400 is stored in the boot memory 408. The boot memory 408 is preferably a non-volatile memory, for example, a memory device with low cost per bit such as a flash memory.

(69) Note that at least the configuration memory 400, the CRC memory 402, the data input/output circuit 404, and the CRC arithmetic circuit 406 are provided on the same chip. The boot memory 408 may be provided on the same chip or provided externally; in the latter case, the boot memory 408 only needs to have a configuration allowing data to be transmitted to and received from the data input/output circuit 404.

(70) FIG. 4C is a schematic view of the CRC arithmetic circuit 406. The CRC arithmetic circuit 406 includes an input register 410, a divisor register 412, an arithmetic circuit 414, and a digit number counter 416.

(71) A divisor necessary for a CRC is stored in the divisor register 412. In the case of an 8-bit CRC, for example, 9-digit data is stored. Here, the leftmost bit of the divisor register 412 is the most significant bit and “1” is input. Note that any of the memory elements illustrated in FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B may be used for the divisor register 412.

(72) The arithmetic circuit 414 includes a plurality of XOR circuits, for example, 9 XOR circuits in the case of an 8-bit CRC, and executes an XOR operation using the upper 9-digit number of the input register 410 and the corresponding number of the divisor register 412. Note that in the case where such a plurality of XOR circuits (each having two inputs) are provided, a reduction in circuit area can be realized by using a 4-bit memory (preferably a read only memory (ROM)) and a plurality of multiplexers.

(73) Although not illustrated, the CRC arithmetic circuit 406 includes other circuits used for arithmetic operation.

(74) Execution process of the CRC will be specifically described below with reference to FIGS. 4B and 4C.

(75) First, data of a row subjected to the CRC is input to the input register 410 from the configuration memory 400 and the CRC memory 402 via the data input/output circuit 404.

(76) When the leftmost bit of the input register 410 is “0”, data is shifted to the left and “1” is stored in the digit number counter 416. The rightmost bit is set to “0”. This processing is repeated until the leftmost bit becomes “1”. Each time data is shifted to the left, “1” is stored in the digit number counter 416, so that the number of times of shifting data (the number of digits) is stored in the digit number counter 416.

(77) For example, data “00100110 . . . ” is input to the input register 410; then, the input data is shifted to the left twice. As a result, the data input to the input register 410 becomes “100110 . . . ”. The number of digits shifted, “2”, is stored in the digit number counter 416.

(78) Then, in the arithmetic circuit 414, an XOR operation is executed using the upper 9-digit number of the input register 410 and the 9-digit number of the divisor register 412. After the arithmetic operation, the result is input to the upper 9 digits of the input register 410. Since the leftmost bit of the input register 410 is “0”, data is shifted to the left and “1” is stored in the digit number counter 416. The rightmost bit is set to “0”. This processing is repeated until the leftmost bit becomes “1”.

(79) After that, the arithmetic operation is performed again in the arithmetic circuit 414. This processing is repeated until the number stored in the digit number counter 416 becomes more than or equal to a predetermined number. For example, in the case where the configuration data is 256-bit data as illustrated in FIG. 4A, the above processing is repeated until the number stored in the digit number counter 416 becomes 256.

(80) Then, the data in the input register 410 is determined. The data in the input register 410 is the remainder of the first number input to the input register 410. It is determined that there is no error if the remainder is 0, while it is determined that there is an error if the remainder is a number other then 0.

(81) Note that one of the causes of errors in a memory is generally a failure in writing data. Such an error occurs at the same rate in an SRAM or the like and in the memory elements illustrated in FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B. Another cause of errors in a memory is a soft error. This error occurs at different rates in an SRAM or the like and in the memory elements illustrated in FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B. As described in Embodiment 1, soft errors are unlikely to occur in the memory elements illustrated in FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B as compared to an SRAM or the like.

(82) Thus, errors can be dealt with on the assumption that they occur due to different causes, which leads to a reduction in unnecessary operations. That is, if an error occurs immediately after data writing, it can be considered as a failure in writing which has occurred in either or both of the configuration memory 400 and the CRC memory 402.

(83) On the other hand, if an error occurs after the success of data writing, it is thought to be mainly caused by a soft error. In that case, only the data of the configuration memory 400 needs to be rewritten because the soft error occurs at a much higher rate in the configuration memory 400 than in the CRC memory 402, which allows efficient processing.

(84) Next, error check processing using a CRC of the method for driving a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 5 and FIG. 6.

(85) First, a configuration will be described with reference to FIG. 5. Here, the number of rows of a memory is n. First, processing is started (start 500), and a loop is started from i=1 (loop start 502).

(86) Then, data of the i-th row is taken out from the boot memory 408 and a remainder is calculated (remainder calculation 504 of the i-th row). After the remainder calculation 504 of the i-th row, data to be input to the i-th row of the configuration memory 400 is input, and data of the calculated remainder is input to the i-th row of the CRC memory 402 (data writing 506 of the i-th row).

(87) Next, an error is detected by a CRC (error detection 508 of the i-th row). The CRC is performed as follows: data of the i-th row of the CRC memory 402 is added to the end of data of the i-th row of the configuration memory 400, the sum is divided by a predetermined divisor, and it is determined whether the remainder is 0. If the remainder is 0, there is no error (branch to N), and there is an error if the remainder is a number other than 0 (branch to Y). In the case where there is no error, the next row is processed. In the case where there is an error, it is determined that a failure in writing has occurred in either the configuration memory 400 or the CRC memory 402, and the remainder calculation 504 of the i-th row, the data writing 506 of the i-th row, and the error detection 508 of the i-th row are performed again and repeated until no error is detected.

(88) The above-mentioned processes are repeated from i=1 to n, and the loop is completed (loop end 510). After the loop end 510, the configuration is completed and transferred to a user mode (processing transfer 512).

(89) Next, a user mode will be described with reference to FIG. 6. Here, the number of rows of a memory is n as in FIG. 5. First, processing is started (user mode start 600), and a loop is started from i=1 (loop start 602).

(90) Note that as described below, in the user mode, the remainder is calculated again if it is determined that there is an error a predetermined number of times or more. Here, the number of times an error is detected is k, and the maximum number of times corresponding to the above predetermined number of times is m. Immediately after the loop start 602, l is input to k (“k=1” 604).

(91) Then, an error is detected by a CRC (error detection 606 of the i-th row). The CRC is performed in a manner similar to that of FIG. 5. If there is no error (branch to N), the next row is processed. If there is an error (branch to Y), data to be input to the i-th row of the configuration memory 400 is input (data writing 608 of the i-th row), and l is added to k (“k+l” 610). At this time, the data of the i-th row of the CRC memory 402 is kept as it is.

(92) Then, it is determined whether an error is detected the maximum number of times, namely, whether k=m (“determination of k=m” 612). In the case where k=m is not satisfied (that is, in the case where the number of times an error is detected does not reach the maximum number of times), the error detection 606 of the i-th row is performed again. In the case where k=m is satisfied (that is, in the case where the number of times an error is detected reaches the maximum number of times), the data of the i-th row is read out from the boot memory 408 and the remainder is calculated (remainder calculation 614 of the i-th row). After the remainder calculation, the data to be input is input to the i-th row of the configuration memory 400 and the calculated remainder is input to the i-th row of the CRC memory 402 (data writing 616 of the i-th row); then, an error is detected again by the CRC (error detection 618 of the i-th row). If there is no error (branch to N), the next row is processed. If there is an error (branch to Y), the remainder calculation 614 of the i-th row is performed again and the above processing is repeated until no error is detected.

(93) Note that the loop from the remainder calculation 614 of the i-th row to the error detection 618 of the i-th row may also have a maximum number of times. If the number of times of the loop reaches the maximum number of times, an error might be caused by a factor other than the above possible factors; accordingly, operation of some or all of the circuits in the semiconductor device may be stopped.

(94) In addition, it is also possible to determine a period from the beginning of an error check of a certain row to the beginning of an error check of the next row. For example, if the period between the beginning and the end of an error check of a certain row is shorter than the predetermined period, an error check of the next row is started after the predetermined period has elapsed from the beginning of an error check of a certain row. On the other hand, if the period between the beginning and the end of an error check of a certain row is longer than or equal to the predetermined period, an error check of the next row is started immediately.

(95) The processing is repeated for i=1 to n; then, the loop is completed (loop end 620). After the loop end, the processing is completed (end 622).

(96) As described above, a CRC can be performed in the method for driving a semiconductor device of one embodiment of the present invention. In a conventional CRC, a remainder needs to be calculated also in a user mode. In the driving method of one embodiment of the present invention, a remainder is calculated in a user mode only when an error is detected a predetermined number of times or more, which is one of the main features of one embodiment of the present invention. Accordingly, the entire processing can be simplified.

(97) Note that in the above processing, upset of a divisor used for calculating a remainder needs to be avoided. Hence, the divisor is preferably stored in a ROM provided inside or outside the semiconductor device. In the configuration, the divisor may be read out from the ROM to be used for calculating a remainder. The data read out in the configuration is preferably stored in any of the memory elements described with reference to FIGS. 1A and 1B, FIG. 2, and FIGS. 3A and 3B.

(98) The above processing is performed in a semiconductor device, a computer, a processor, or the like with use of a computer program stored in a read only memory which is provided inside or outside the semiconductor device. Note that the computer program is transmitted or received through a communication line in some cases. In other cases, the computer program is transmitted as needed, or relayed through a server or the like.

(99) This application is based on Japanese Patent Application serial No. 2012-100190 filed with Japan Patent Office on Apr. 25, 2012, the entire contents of which are hereby incorporated by reference.