The present invention generally relates to nanoscale wires for use in sensors and other applications. In various embodiments, a probe comprising a nanotube (or other nanoscale wire) is provided that can be directly inserted into a cell to determine a property of the cell, e.g., an electrical property. In some cases, only the tip of the nanoscale wire is inserted into the cell; this tip may be very small relative to the cell, allowing for very precise study. In some aspects, the tip of the probe is held by a holding member positioned on a substrate, e.g., at an angle, which makes it easier for the probe to be inserted into the cell. The nanoscale wire may also be connected to electrodes and/or form part of a transistor, such that a property of the nanoscale wire, and thus of the cell, may be determined. Such probes may also be useful for studying other samples besides cells. Other aspects of the invention are generally directed to methods of making or using such probes, kits involving such probes, devices involving such probes, or the like.

Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.

The invention is a field-effect transistor with a channel consisting of a thin sheet of one or more atomic layers of lateral heterostructures based on hybridized graphene. The role of lateral heterostructures is to modify the energy gap in the channel so as to enable the effective operation of the transistor in all bias regions. This solution solves the problem of the missing bandgap in single-layer and multi-layer graphene, which does not allow the fabrication of transistors that can be efficiently switched off. The possibility of fabricating lateral heterostructures, with patterns of domains with different energy dispersion relations, enables the realization of field-effect transistors with additional functionalities with respect to common transistors.

Provided is a planar nano-oscillator array having phase locking function, including two or more planar nano-oscillators which are arranged in parallel. The two oscillators are connected by planar resistors and capacitors, and a structure thereof includes: electrodes; respectively introducing two pairs of laterally arranged parallel insulation notch grooves into two-dimensional electron gas layers, so as to form oscillation channels; vertically disposing separating insulation notch grooves, so that a planar resistor A with low resistance which is connected to the electrode is formed on the left side, and a planar resistor B with low resistance which is connected to the electrode is formed on the right side; and arranging, between the two oscillators, an insulation capacitor notch groove which is parallel to the oscillation channels, insulating materials having a high dielectric constant being filled therein.

The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO.sub.2 region.

An integrated circuit device includes: a rear insulating layer; a nanosheet stacked structure arranged on the rear insulating layer and including a plurality of nanosheets; a pair of source/drain regions positioned on sides of the nanosheet stacked structure in a first horizontal direction; a gate electrode extending in a second horizontal direction intersecting the first horizontal direction, on the nanosheet stacked structure; a contact plug connected to at least one of the pair of source/drain regions; a rear contact plug passing through the rear insulating layer and connected to at least one of the pair of source/drain regions; and a spacer layer including a contact spacer layer surrounding part of a side surface of the rear contact plug.

The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO.sub.2 region.

The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO.sub.2 region.

Operating a double-sided double-base bipolar junction transistor. One example is a method of operating a switch assembly, the method comprising: blocking current flow from an upper terminal of the switch assembly to a lower terminal by a transistor; and then responsive to assertion of a conduction signal, conducting a first load current from the upper terminal to a lower terminal. The conducting the first load current may be by: closing an upper-main FET coupled between the upper terminal and an upper collector-emitter of the transistor; closing a lower-main FET coupled between a lower collector-emitter of the transistor and the lower terminal; driving a first turn-on current to an upper base of the transistor from an upper current source; and then providing a first steady-state current to the upper base from the upper current source, the first steady-state current lower than the first turn-on current.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. The floating body region is surrounded on all sides by gate region and may include a nanosheet FET, a multi-bridge-channel (MBC) FET, a nanoribbon FET or a nanowire FET. The floating body region is configured to have at least first and second stable states.