A display device includes a substrate including a first display area, a second display area, and a non-display area, a plurality of first signal lines extending in a first direction and disposed in the first display area, a plurality of second signal lines extending from the non-display area in the first direction and disposed in the second display area, a plurality of connection lines connected to the first signal lines and extending to the non-display area via the first display area and the second display area, and a test circuit portion disposed in the non-display area. At least some of the plurality of connection lines and at least some of the second signal lines are electrically the test circuit portion.

This invention provides an asymmetric pads structure using at a scribe line of a wafer, comprising a test element device electrically connected to a first pad and a second pad separately, wherein a first spacing between the second pad and the test element device is sufficient to accommodate the second pad of an another asymmetric pads structure. So, two neighboring asymmetric pads structures may cross to each other to form a cross configuration.

An accelerated test for applying a high voltage is performed without reducing a manufacturing yield of a semiconductor device using a wide gap semiconductor material. The technical idea in the embodiment is, for example, an idea of performing the accelerated test in the state of a semiconductor wafer to distinguish a latent defect as illustrated in FIG. 4. That is, the technical idea in the embodiment is to perform the accelerated test on a semiconductor chip containing a wide bandgap semiconductor material as a main component not in the state of a semiconductor chip but in the state of the semiconductor wafer.

A driving back plate, a display panel, and a preparation method therefor. The driving back plate includes a plurality of pixel driving units. At least one of the pixel driving units includes a main electrode pair and at least one redundant electrode pair. A second electrode of the main electrode pair, a first electrode of the main electrode pair, a first electrode of a redundant electrode pair, and a second electrode of the redundant electrode pair are arranged sequentially in a first direction. At least one of the pixel driving units includes a connection line. The connection line includes a cutting portion. A signal on the connection line is configured to be input between the redundant electrode pair and the cutting portion.

A semiconductor structure includes vertical conductive features disposed over a substrate, and horizontal conductive features disposed over the vertical conductive features. The horizontal conductive features include first and second conductive lines respectively electrically connected to the first and second vertical conductive features, a first conductive segment disposed between the first vertical conductive feature and the second conductive line, and a second conductive segment disposed between the first conductive line and the second vertical conductive feature. The first conductive segment is electrically isolated from the vertical conductive features. The second conductive segment is electrically isolated from the vertical conductive features.

A non-contact processing device and a non-contact processing method are used to perform a processing procedure on a solid structure. The non-contact processing device of the invention uses an electromagnetic radiation source to provide energy to the solid structure to cause qualitative changes or defects in the solid structure, that is, to form a modified layer. A separation energy source is used to apply a separation energy on the solid structure with the modified layer in a non-contact manner. With stress, structural strength, lattice pattern or hardness of the modified layer being different from that of other non-processing areas, the solid structure can be rapidly separated or thinned at the modified layer.

Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.

An apparatus for chemical mechanical polishing of a wafer includes a process chamber and a rotatable platen disposed inside the process chamber. A polishing pad is disposed on the platen and a wafer carrier is disposed on the platen. A slurry supply port is configured to supply slurry on the platen. A process controller is configured to control operation of the apparatus. A set of microphones is disposed inside the process chamber. The set of microphones is arranged to detect sound in the process chamber during operation of the apparatus and transmit an electrical signal corresponding to the detected sound. A signal processor is configured to receive the electrical signal from the set of microphones, process the electrical signal to enable detection of an event during operation of the apparatus, and in response to detecting the event, transmit a feedback signal to the process controller. The process controller is further configured to receive the feedback signal and initiate an action based on the received feedback signal.

A power semiconductor module (34), comprising a substrate (12) which carries a plurality of power semiconductor devices (10), wherein the plurality of power semiconductor devices (10) comprises a first group of power semiconductor devices (10) and a second group of at least one power semiconductor device (10). The first group of power semiconductor devices (10) consists of at least two non-damaged power semiconductor devices (10b, 10c), and the second group of power semiconductor devices (10) consists of at least one damaged power semiconductor device (10a). The at least two non-damaged power semiconductor devices (10b, 10c) are electrically interconnected in a parallel configuration, and the second group of at least one power semiconductor device (10) is electrically separated from the members of the first group of power semiconductor devices (10). The disclosure further relates to an electrical converter and a method for manufacturing a power semiconductor module (34).

One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.