A protective device for an imager which is contained within a housing and in which the imager is aligned with an opening in the housing. The protective device includes a cover which overlies the housing opening and is manually detachably secured to the housing by three or more resilient clips. A plurality of openings are formed through the cover to enable operation of the imager.

The pixel structure includes a plurality of pixel units each including a first sub-pixel with a first color, having a first adjoining edge of a first length and a second adjoining edge of a second length; a second sub-pixel with a second color, having a first adjoining edge of the first length and a second adjoining edge of a third length; and a third sub-pixel with a third color, having a first adjoining edge of the second length and a second adjoining edge of the third length. In each pixel unit, the first adjoining edge of the first sub-pixel is adjoined to the first adjoining edge of the second sub-pixel, the second adjoining edge of the first sub-pixel is adjoined to the first adjoining edge of the third sub-pixel, and the second adjoining edge of the second sub-pixel is adjoined to the second adjoining edge of the third sub-pixel.

An image sensor includes: a plurality of light-receiving elements that receive light from a subject and are arranged in a 2-dimensional form; a detection unit that detects a movement amount of a projected image of the subject projected to the plurality of light-receiving elements arranged in the 2-dimensional form; and a light-receiving element control unit that adaptively controls a timing at which pixel data is read from the plurality of light-receiving elements arranged in the 2-dimensional form for each line according to the movement amount.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

A display device and a method for fabricating the same are provided. The display device comprises pixels connected to scan lines, and to data lines crossing the scan lines, each of the pixels including a light emitting element, and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the first transistor including a first active layer having an oxide semiconductor, and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn).

Quantum dot layers and display devices including quantum dot layers are described. In an embodiment the quantum dot layer includes quantum dots with metal oxide coatings to adjust the spacing between adjacent quantum dots. In an embodiment, the metal oxide coatings may create a charge transporting matrix, be QD-LED compatible.

The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.

An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.

An electronic device comprising a laminated structure including a first semiconductor chip and a second semiconductor chip is disclosed. In one example, the first semiconductor chip includes a sensor portion in which sensors are arranged, and the second semiconductor chip includes a signal processing portion in which signals obtained by the sensors are processed. The signal processing portion includes a high breakdown voltage transistor circuit and a low breakdown voltage transistor circuit. The low breakdown voltage transistor circuit includes a depletion-type field effect transistor.

The curved image sensor may include: a first substrate including a plurality of photoelectric conversion elements and having a curved first surface; a bonding pattern formed over a second surface opposite to the first surface of the first substrate, formed along an edge of the first substrate, and having an opening; a second substrate bonded to the second surface of the first substrate by the bonding pattern; and a sealing material filling the opening so that a cavity defined by the first substrate, the second substrate, and the bonding pattern is sealed by the sealing material.