A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.

A channel driver circuit includes a differential module and a driver module. In some examples, the channel driver circuit also includes a sigma-delta module. The differential module receives, via a single node of a load, a channel driving signal that is provided to the load at the single node (e.g., that is based on an electrical characteristic of the load) and generates an analog error signal that is based on the channel driving signal and a reference signal. The driver module is coupled to the differential module and generates the channel driving signal based on the analog error signal or a digital error signal corresponding to the analog error signal and transmits the channel driving signal via the single node to the load. The channel driver circuit simultaneously transmits the channel driving signal to the load at the single node and senses the channel driving signal at the single node.

LED drive control circuitry according to one embodiment outputs an LED drive control signal serving as driving a light emitting diode included in a photocoupler that performs insulation communication in synchronization with a reference clock signal. The LED drive control circuit includes a duty cycle changer that changes a duty cycle of the LED drive control signal in accordance with the reference clock signal and a signal synchronized with the reference clock signal.

An amplifier circuit includes a resistor divider (R.sub.REF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d.sub.1, d.sub.2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I.sub.REF) connected or connectable to the first main node (a). The resistor divider (R.sub.REF) comprises two arrays of addressable switch elements controllable by a feedback signal (s.sub.FB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T.sub.1, T.sub.2), wherein source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b), gate terminals of the transistors (T.sub.1, T.sub.2) are connected to input signals (v.sub.1, v.sub.2), drain terminals of the transistors (T.sub.1, T.sub.2) are connected to current sources (I.sub.1, I.sub.2), and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the readout nodes (d.sub.1, d.sub.2). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

A digital filter for filtering a pulse density modulation (PDM) signal is presented. The filter has a first filter circuit to receive an input signal and to provide a filtered input signal at successive time steps which include a first filtered value at the first time step and a second filtered value at a second time step. The filter also has a quantizer to provide an output signal comprising output values at successive time steps and a filter variable circuit with a first multiplication circuit to receive the first filter variable, and divide the first filter variable by a first gain factor and a first summing circuit configured to receive the divided first filter variable, receive the output signal, and add the divided first filter variable and the first output value and a second multiplication circuit and a delay circuit.

An interleaved cascaded integrator-comb (“CIC”) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.

An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

A variety of methods, controllers and electric machine systems are described that facilitate pulsed control of electric machines (e.g., electric motors and generators) to improve the machine's energy conversion efficiency. Under selected operating conditions, the electric machine is intermittently driven (pulsed). The pulsed operation causes the output of the electric machine to alternate between a first output level and a second output level that is lower than the first output level. The output levels are selected such that at least one of the electric machine and a system that includes the electric machine has a higher energy conversion efficiency during the pulsed operation than the electric machine would have when operated at a third output level that would be required to drive the electric machine in a continuous manner to deliver the desired output. In some embodiments, the second output level is zero torque.

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L error feedback modulator (EFM) stages, wherein the jth EFM stage is configured to receive as an input the sum of the error of the preceding EFM stage and a high amplitude dither signal derived from the error of the kth EFM stage, where 1≤j≤k≤L.