A resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure through the plurality of insulating layers and the plurality of conductive layers; a plurality of insulating patterns formed on a sidewall of each of the plurality of interlayer insulating layers within the hole; a channel layer formed along a sidewall of each of the plurality of conductive layers within the hole and a sidewall of each of the plurality of the insulating patterns within the hole, wherein the channel layer includes convex regions that are adjacent to the insulating patterns and are convexly formed in relation to a central portion of the hole and includes concave regions that are adjacent to the plurality of conductive layers and are concavely formed in relation to the central portion of the hole.

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a plurality of insulating layers spaced apart from each other in a stacking direction, a slit insulating layer passing through the plurality of insulating layers, a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction, a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction, a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers, and a second variable resistance layer surrounding a sidewall of the conductive pillar.

A memory device includes a selector and a memory cell. The selector includes a first electrode layer, a second electrode layer and a selector layer between the first electrode and the second electrode. The selector layer includes a first element selected from a group consisting of silicon (Si), germanium (Ge), tin (Sn) and aluminum (Al), a second element selected from a group consisting of oxygen (O) and nitrogen (N), and a third element selected from a group consisting of tellurium (Te), selenium (Se) and antimony (Sb).

There are provided a resistive memory device and a manufacturing method of the resistive memory device. The resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure in a vertical direction; and a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole.

A semiconductor memory device may include one or more memory cells, and each of the memory cells may include a memory unit for storing data; and a selection element unit electrically connected to the memory unit and including a first electrode layer, a second electrode layer, and a selection element layer that includes an insulating material layer doped with a dopant and is interposed between the first electrode layer and the second electrode layer, wherein the insulating material layer has a two-dimensional crystalline structure.

A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

A semiconductor memory device includes a substrate and a transistor disposed on the substrate. The transistor includes a source doped region, a drain doped region, a channel region, and a gate over the channel region. A data storage region is in proximity to the transistor and recessed into the substrate. The data storage region includes a ridge and a V-shaped groove. A bottom electrode layer conformally covers the ridge and V-shaped groove within the data storage region. A resistive-switching layer conformally covers the bottom electrode layer. A top electrode layer covers the resistive-switching layer.

A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

Provided are a capacitor and a semiconductor device including the same. The capacitor includes: a dielectric layer having a perovskite crystal structure; and first and second electrodes spaced apart from each other with the dielectric layer therebetween. At least one of the first and second electrodes includes a metallic layer having a perovskite crystal structure, a first ionic layer having ionic properties, and a semiconductor layer.