Embodiments of the present application relate to a resistive memory device and a preparation method thereof. The preparation method includes: providing a base; forming bit line trenches in the base; forming a resistive material layer on a sidewall and the bottom of the bit line trench; and forming a bit line structure in the bit line trench through filling, wherein a variable resistor structure includes the bit line structure and the resistive material layer.

An array substrate, a display panel, and a display device are provided. The array substrate includes a substrate, a semiconductor layer, a gate insulation layer, a gate layer, an interlayer insulation layer, and data lines, wherein the semiconductor layer is directly below the data lines.

A resistive random access memory (RRAM) device includes a plurality of memory cells, each of at least a subset of the memory cells including first and second electrodes and an organic thin film compound mixed with silver perchlorate (AgClO.sub.4) salt as a base layer that is incorporated with a prescribed quantity of inorganic metal oxide molecules using vapor-phase infiltration (VPI), the base layer being formed on an upper surface of the first electrode and the second electrode being formed on an upper surface of the base layer. Resistive switching characteristics of the RRAM device are controlled as a function of a concentration of AgClO.sub.4 salt in the base layer. A variation of device switching parameters is controlled as a function of an amount of infiltrated metal oxide molecules in the base layer.

A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Disclosed is a synaptic device, a reservoir computing device using the synaptic device, and a reservoir computing method using the reservoir computing device. The synaptic device includes a substrate and a plurality of units cells on the substrate, wherein the unit cells each include a channel layer and a first electrode and second electrode intersecting the channel layer, wherein the first electrode and the second electrode are spaced apart from each other, and define a gap region exposing a portion of the channel layer, and the channel layer includes a 2-dimensional semiconductor material or a 2-dimensional ferroelectric material.

Circuits and methods that provide wider bandwidth and smaller IM inductances for phase change material (PCM) based RF switch networks. The present invention recognizes that it is beneficial to consider the total high parasitic capacitance to ground of the various PCM switches in an RF switch network as constituting two or more separate capacitive contributions. This leads to several “split capacitance” concepts, including signal-path splitting, switch-block splitting, stacked-switch splitting, and splitting parasitic capacitances due to layout discontinuities, in which compensating impedance matching inductances are inserted between additive capacitances.

The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.

The present disclosure relates to a switch system that provides a control method for switches based on dual-phase materials. The disclosed switch system includes a heat resistor, a power management (PM) unit configured to provide a control voltage at a voltage port coupled to the heat resistor, and a phase-change-based switch. Herein, the heat resistor is underneath the phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the phase-change-based switch. The phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the heat resistor. The control voltage provided by the PM unit contains waveform information of target heat energy required for switching on and off the phase-change-based switch.

The present disclosure relates to a switch system that provides a control method for switches based on dual-phase materials. The disclosed switch system includes a heat resistor, a power management (PM) unit configured to provide a control voltage at a voltage port coupled to the heat resistor, and a phase-change-based switch. Herein, the heat resistor is underneath the phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the phase-change-based switch. The phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the heat resistor. The control voltage provided by the PM unit contains waveform information of target heat energy required for switching on and off the phase-change-based switch.

A phase change switch device includes a phase change material and a heater device thermally coupled to the phase change material. The heater device is configured to have a first electrical resistance in a first state where current is applied to the heater device for heating the phase change material, and have a second electrical resistance higher than the first electrical resistance in a second state outside heating phases of the heater device.