A semiconductor device may include a semiconductor substrate, a wire placed along at least a portion of a perimeter of the semiconductor substrate, and processing circuitry connected to the wire, the processing circuitry to, based on a signal from the wire, determine whether or not the semiconductor device is damaged.

Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates.

A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation.

A probe card for testing or trimming or programming a semiconductor wafer including a first die including a first integrated circuit having a trimmable or programmable component. The probe card including at least one probe arranged to make electrical contact with at least one probe pad arranged on the wafer. The at least one probe pad being electrically connected to the trimmable or programmable component and being arranged in a saw street of the wafer.

A probe card for testing or trimming or programming a semiconductor wafer having a first die including a first integrated circuit having a trimmable or programmable component. The probe card includes at least one probe arranged to make electrical contact with a contact pad of a second die arranged adjacent to the first die. The contact pad of the second die being configured to act as a probe pad and being electrically connected to the trimmable or programmable component of the first die.

Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG. The physical contacting to the topside of the wafer is noncontaminating and noninvasive to the semiconductor layers.

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation.

A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.

A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.