This disclosure describes an elastic multi-contact probe that includes conductive strips each of which comprises a conductive elastomer; dielectric strips formed on a back surface of a respective conductive strip; and a layer of a thermoplastic formed on back surfaces of the dielectric strips. The disclosure also describes a method that includes measuring a first I-V curve between a pair of inner probes of the an elastic multi-contact probe based on a first current applied to a pair of outer probes; determining a first slope of a linear region of the first I-V curve; measuring a second I-V curve between the pair of inner probes based on a second current applied to the pair of inner probes; determining a second slope of a linear region of the second I-V curve; and calculating a sheet resistance and a contact resistivity of the semiconductor material based on the first and second slopes.

An electronic device, a signal validator, and a method for signal validation are provided. The electronic device includes a circuit board generating a plurality of signals and a signal validator. The signal validator records a current voltage level of each signal as a sequence code and records a time interval between the sequence code and a previous sequence code as a delay time corresponding to the sequence code when a voltage level of one of the plurality of signals changes. The signal validator sequentially determines whether the sequence code matches with a prearranged sequence code. When the sequence code matches with the prearranged sequence code, the signal validator determines whether each delay time corresponding to each sequence code exceeds a predetermined delay time. When the delay time is less than the predetermined delay time, the signal validator determines that the plurality of signals passes signal validation.

A method for determining a CET mapping characterizing the capture and emission time of traps in a transistor for a given stress voltage and a given temperature, called an optimal CET mapping, this determination being made from an experimental measurement of the time course of the change in the threshold voltage V_TH for the same stress voltage and the same temperature and from a distribution function of the traps, the distribution function may be defined by N_par parameters. More particularly, the method implements a genetic algorithm whose parameters are regularly updated in order to optimize the computation time while decreasing the risk of reaching a local minimum in the determination of the optimal CET mapping.

An inspection system includes an inspection device that includes a stage on which a substrate is mounted and inspects the substrate on the stage, a temperature adjustment mechanism that adjusts the temperature of the stage, a substrate accommodating part, a temperature measurement substrate standby part that makes a temperature measurement substrate wait, a transfer unit that transfers the substrate and the temperature measurement substrate onto the stage, and a camera used for aligning the substrate on the stage. The temperature measurement substrate includes, on the surface thereof, a temperature measurement member whose state changes depending on the temperature. The transfer unit transfers the temperature measurement substrate onto the stage, the camera images the temperature measurement member, and the temperature of the temperature measurement substrate is measured from a change in the state of the temperature measurement member.

A manufacturing method of an interposer for disposing a semiconductor chip and an external terminal at two opposing sides includes the following steps. An active device is bonded to a first redistribution structure, wherein an active surface of the active device is in electrical contact with the first redistribution structure. A dielectric layer is formed on the first redistribution structure to encapsulate the active device. A second redistribution structure is formed over the dielectric layer to be electrically coupled to the first redistribution structure, wherein the first conductive pattern of the first redistribution structure is formed according to a first design rule to be finer than a second conductive pattern of the second redistribution structure formed according to a second design rule, the semiconductor chip and the external terminal are configured to be respectively disposed on the first conductive pattern and the second conductive pattern.

A connecting device for inspection includes a probe head (30) configured to hold electric contacts (10) and optical contacts (20) such that tip ends of the respective contacts are exposed on a lower surface of the probe head (30), and a transformer (40) including connecting wires (41) arranged therein and optical wires (42) penetrating therethrough. The respective proximal ends of the electric contacts (10) and the optical contacts (20) are exposed on an upper surface of the probe head (30), and tip ends on one side of the connecting wires (41) electrically connected to the proximal ends of the electric contacts (10) and connecting ends of the optical wires (42) optically connected to the proximal ends of the optical contacts (20) are arranged in a lower surface of the transformer (40). A positional relationship between the tip end of the respective electric contacts (10) and the tip end of the respective optical contacts (20) on the lower surface of the probe head (30) corresponds to a positional relationship between an electrical signal terminal and an optical signal terminal of a semiconductor device.

A device for processing a multiplicity of semiconductor chips in a wafer assemblage includes an electrically conductive carrier for contacting rear contacts of the semiconductor chips, an electrically conductive film for contacting front contacts of the semiconductor chips that are situated opposite the rear contacts, and a squeegee, which is displaceable relative to the film and is configured to press a region of the film in the direction toward the carrier.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

A semiconductor element encompasses a first external electrode on an upper surface side of a semiconductor chip, a second external electrode, spaced apart from the first external electrode, provided in parallel with the first external electrode; and a protective film covering the first and second external electrodes, having first and second windows to expose portions of upper surfaces of the first and second external electrodes, respectively. Planar patterns of the first and second windows are in two-fold rotational symmetry with respect to a center point of an area including the first and second external electrodes and to be asymmetric with respect to a center line between the first and second external electrodes.

The disclosure discloses an IGBT module reliability evaluation method and device based on bonding wire degradation, which belong to the field of IGBT reliability evaluation. The realization of the method includes: obtaining a relationship between a IGBT chip conduction voltage drop U.sub.ces and an operating current I.sub.c along with a chip junction temperature T.sub.c; for an IGBT module under test, obtaining the conduction voltage drop U.sub.ces-c of the IGBT chip through the operating current I.sub.c and the chip junction temperature T.sub.c; obtaining an external conduction voltage drop U.sub.ces-m of the IGBT module by using a voltmeter; performing subtraction to obtain a voltage drop at a junction of a IGBT chip and a bonding wire, and combining the operating current to obtain a resistance at the junction; determining that the IGBT module has failed when the resistance at the junction increases to 5% of an equivalent impedance of the IGBT module.