The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

A contact position of a probe needle with respect to electrode pads 71 to 75 of a semiconductor device is inspected in advance when performing an inspection by a prober on the semiconductor device formed on a wafer W placed on a stage 11. A reticle 31 on which shapes 61 to 65 indicating positions of the probe needles are formed is placed instead of the probe needles at a position where the probe needles are arranged. The semiconductor device formed on the wafer W is imaged by the imaging unit 33 through the reticle 31. A positional relationship between the shapes formed on the reticle 31 and the electrode pads 71 to 75 is analyzed from the image. When necessary, a position of the stage 11 is adjusted such that centers of the shapes 61 to 65 and centers of the electrode pad 71 to 75 are coincident.

A semiconductor apparatus may include a unit chip and a characteristic measurement circuit configured to include a plurality of unit elements for test and to output electrical characteristic information of the plurality of unit elements for test.

A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crowns (40) are maintained relatively coplanar by the engagement of at least one flange (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.

Disclosed herein is a method of detecting an arc generated in a semiconductor device. The method may comprise: performing a processing process for a substrate processing and collecting data according to the processing process; separating the collected data by setting sections; obtaining an average value and a standard deviation of the data separated for each section; and setting an upper limit and a lower limit for detecting the arc using the average value and the standard deviation.

Disclosed are an IGBT-module condition monitoring equipment and method. The IGBT-module condition monitoring equipment includes an IGBT module, a gate turning-on voltage overshoot monitoring module, a driving circuit, a bond wire state judging module, and a signal acquisition module. The breakage condition of bond wires is obtained by comparing a monitored actual gate turning-on voltage overshoot with a preset reference gate turning-on voltage overshoot threshold. The present invention solves the problem encountered in monitoring the aging of IGBT bond wires in power electronic converters. By characterizing the bond wire detachment with the gate turning-on voltage overshoot, the slight aging of the detached bond wires can be monitored without disturbing the operation, which is high in resolution and free of invasiveness and enables real-time online monitoring at high sampling rate and low cost, showing great significance in the monitoring of the IGBT and the reliability evaluation of power electronic converters.

A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.

A semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the semiconductor device including an electrode portion having a potential other than a gate potential, and an electrode pad that is disposed on a front face of a semiconductor substrate, wherein the electrode pad is used as a terminal to apply a predetermined voltage to gate insulator films, in screening that is executed by applying the predetermined voltage to the gate insulator films respectively in contact with the gate electrode connected to the electrode pad and that is executed before the electrode pad is short-circuited to the electrode portion.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

An object is to provide a technique capable of creating a precise measurement condition in a facilitated manner relating to an electrical characteristic inspection for a semiconductor device. An electrical characteristic inspection device includes a storage unit configured to store a measurement condition of the semiconductor device being an inspection subject, a control unit configured to read out the measurement condition corresponding to inspection contents to be executed from the storage unit, an inductive inductance control circuit unit configured to set inductive inductance for the semiconductor device, and a floating inductance control circuit unit configured to set floating inductance for the semiconductor device. Based on the measurement condition read out from the storage unit, the control unit is configured to adjust the inductive inductance by controlling the inductive inductance control circuit unit, and adjust the floating inductance by controlling the floating inductance control circuit unit.