A power supply device for a test equipment, test equipment having a power supply device and a method for operating a power supply device are described. The power supply device is configured for an at least partly capacitive load and has an output voltage provider configured to generate a target voltage, which is energized by an input supply voltage provided at an input of the power supply, wherein the target voltage generates an output supply voltage at the capacitive load, when the capacitive load is connected to an output of the power supply and a supply current monitor configured to monitor supply current flowing into the input of the power supply and to temporarily reduce the target voltage generating the output supply voltage, if a current value of the supply current exceeds a first predetermined threshold.

Disclosed is a signal transmission circuit device (200) including a feedback signal transmission unit (210) that feeds back a control output signal (Sout) as a feedback signal (Sf) to an input side circuit (200A). A logical comparison circuit (212) detects mismatch between input and output by performing logical comparison between a control input signal (Sin) and the feedback signal (Sf). When a state of mismatch between input and output occurs, a first pulse generating circuit (202) or a second pulse generating circuit (204) outputs a first correction signal (Sa1) or a second correction signal (Sa2) corresponding to a potential (high level or low level) of the control input signal (Sin), and corrects the control output signal (Sout) to the same potential (high level or low level) as the control input signal (Sin). With such configuration, the mismatch

Disclosed is a signal transmission circuit device (200) including a feedback signal transmission unit (210) that feeds back a control output signal (Sout) as a feedback signal (Sf) to an input side circuit (200A). A logical comparison circuit (212) detects mismatch between input and output by performing logical comparison between a control input signal (Sin) and the feedback signal (Sf). When a state of mismatch between input and output occurs, a first pulse generating circuit (202) or a second pulse generating circuit (204) outputs a first correction signal (Sa1) or a second correction signal (Sa2) corresponding to a potential (high level or low level) of the control input signal (Sin), and corrects the control output signal (Sout) to the same potential (high level or low level) as the control input signal (Sin). With such configuration, the mismatch

A drive circuit for a power semiconductor element according to the present disclosure includes: a control command unit that outputs a turn-on command for a power semiconductor element; a gate voltage detection unit that detects a gate voltage applied to a gate terminal after the control command unit outputs the turn-on command; a differentiator that subjects the gate voltage detected by the gate voltage detection unit to time differentiation; and a determination unit that determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not.

A drive circuit for a power semiconductor element according to the present disclosure includes: a control command unit that outputs a turn-on command for a power semiconductor element; a gate voltage detection unit that detects a gate voltage applied to a gate terminal after the control command unit outputs the turn-on command; a differentiator that subjects the gate voltage detected by the gate voltage detection unit to time differentiation; and a determination unit that determines, based on the gate voltage detected by the gate voltage detection unit and a differential value by the differentiator, whether the power semiconductor element is in a short-circuit state or not.

A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

A method to establish a degradation state of electrical connections in a power semiconductor device comprising:

measuring at least two voltage drop values under two respective current values for the same temperature value. The two current values are strictly different or the measurements are made under two distinct gate levels of a transistor;

saving the measured values as calibration data;

monitoring operational conditions of said power semiconductor device;

measuring at least two voltage drop values under respective same current values as preceding, and at two respective moments during which the monitored operational conditions corresponding to two respective predefined sets of criteria related to states of operation and to a common temperature;

saving the at least two values as operational data;

calculating a numerical index in a manner to estimate a degradation state of said power semiconductor device.