A test arrangement for testing a power electronics controller. An intermediate network current in the electrical intermediate network is reduced in that the intermediate network current flowing in the intermediate network is determined by the controller and the controller changes at least one control value of at least one of the load-side power electronics modules in such a way that the intermediate network current is reduced when the interface of the load-side power electronics module is applied with the modified control value.

A system for testing a plurality of electrical circuits includes a first remote cooperative testing device for selectively and electrically coupling a first electrical circuit and a second electrical circuit of the plurality of electrical circuits at a first node, and a second remote cooperative testing device for selectively and electrically coupling the first and second electrical circuits at a second node. A testing circuit is formed between the first node and the second node by the first and second remote cooperative testing devices.

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

A system, apparatus, and method for testing a squib circuit. An electrical signature of the squib circuit is monitored when a test switch in the squib circuit is activated. The electrical signature of the squib circuit is based on characterizing resistors electrically connected to squibs in the squib circuit in which each characterizing resistor in the characterizing resistors has a resistance value. A health of each squib in the squib circuit is determined based on the electrical signature of the squib circuit.

An adapter device for measuring the signal power in a coaxial connection from an RFID reading device to a second device is provided, wherein the adapter device has a first coaxial connector and a second coaxial connector for deploying the adapter device in the coaxial connection and a measuring unit that is configured to determine the signal power of a signal propagating from the first coaxial connector to the second coaxial connector and/or vice versa, In this respect, the first coaxial connector and the second coaxial connector are releasable so that the adapter device can selectively be deployed in the coaxial connection or can be removed therefrom.

The systems include a transmitter, a receiver, a signal sampler and a cable length calculation unit. The transmitter is configured to transmit a plurality of data symbols at a first data rate via a wired data communication link, and the receiver is configured to receive a reflection signal. The signal sampler is configured to sample the received reflection signal using a phase shift number of shifting sampling phases to generate reflection samples, and combine the reflection samples with different sampling phases to generate a series of reflection samples corresponding to a second data rate higher than the first data rate. The cable length calculation unit is configured to determine a delay parameter from the series of reflection samples, and generate an estimate of a length of the data communication link.

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

A circuit comparing method includes the following operations: detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a first circuit diagram; detecting several connection relationships between all starting points and all ending points corresponding to all starting points of a second circuit diagram; determining at least one difference between several connection relationships of the first circuit diagram and several connection relationships of the second circuit diagram; and outputting the at least one difference.

System and method, in the field of device control, for detecting and processing one or more deviations from an acceptable electrical behavior in an electrical device are provided here. The system may include a sampling unit for receiving at least one activity indication, a storage to store acceptable values related to the acceptable electrical behavior, an active time measurement unit to receive the activity indication and measure an active time duration, an inactive time measurement unit to receive the activity indication and measure an inactive time duration and a deviation processor to compute values derived from the activity indication, the active time duration and the inactive time duration, detect and analyze one or more deviations between the acceptable values and the derived values.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.