An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

A parallel analog circuit automatic optimization method based on genetic algorithm and machine learning comprises global optimization based on genetic algorithm and local optimization based on machine learning, with the global optimization and the local optimization performed alternately. The global optimization based on genetic algorithm utilizes parallel SPICE simulations to improve the optimization efficiency while guaranteeing the optimization accuracy, combined with parallel computing. The local optimization based on machine learning establishes a machine learning model near the global optimal point obtained by the global optimization, and uses the machine learning model to replace the SPICE simulator, thus reducing the time costs brought by a large number of simulations.

Methods and systems for measuring semiconductor structures based on a trained scanning conditional measurement model are described herein. A scanning conditional model is trained based on Design Of Experiments (DOE) measurement data associated with known values of one or more parameters of interest and a set of perturbed values of the one or more parameters of interest. The trained conditional model minimizes the output of an error function characterizing the error between the known values of the perturbed values of the one or more parameters of interest for the given DOE measurement data. During inference, an error value associated with each candidate value of one or more parameters of interest is determined by the trained scanning conditional measurement model. The estimated value of the parameter of interest is the candidate value of the parameter of interest associated with the minimum error value.

Methods and systems for measuring semiconductor structures based on a trained scanning conditional measurement model are described herein. A scanning conditional model is trained based on Design Of Experiments (DOE) measurement data associated with known values of one or more parameters of interest and a set of perturbed values of the one or more parameters of interest. The trained conditional model minimizes the output of an error function characterizing the error between the known values of the perturbed values of the one or more parameters of interest for the given DOE measurement data. During inference, an error value associated with each candidate value of one or more parameters of interest is determined by the trained scanning conditional measurement model. The estimated value of the parameter of interest is the candidate value of the parameter of interest associated with the minimum error value.

A model management apparatus for managing a power grid model having, as a model value, a parameter of a power grid connecting a plurality of sites includes: a storage unit configured to store the model value; a monitoring unit configured to acquire a measured value from each site in the power grid; and a model correction unit configured to calculate a parameter in the power grid based on the measured value obtained from the monitoring unit, and correct the model value using the calculated parameter.

A model management apparatus for managing a power grid model having, as a model value, a parameter of a power grid connecting a plurality of sites includes: a storage unit configured to store the model value; a monitoring unit configured to acquire a measured value from each site in the power grid; and a model correction unit configured to calculate a parameter in the power grid based on the measured value obtained from the monitoring unit, and correct the model value using the calculated parameter.

Testbeds for battery management systems (BMSs) and/or batteries, as well as methods of using the same, are provided. A testbed can be a control-hardware-in-the-loop (CHIL) testbed and can include a simulation bench including a battery cell simulator, a temperature simulator, and/or a real-time simulator. The simulator bench can further include a programmable power supply, a relay, a resistor, and/or a communication protocol.

It is provided an encryption hybrid model SI simulation method based on an ADS and an HSPICE. The method includes: extracting step response data of a TX end chip encryption model by using HSPICE transient simulation; externally generating a random code signal; and taking the extracted step response data and the random code signal as input sources of ADS channel simulation, to realize active simulation to the encryption hybrid model.

A transistor using patterned metamaterial electrode manipulating electromagnetic waves to achieve matched phase velocity on the input and output ports. A design method is taught wherein the layout of the electrodes can be designed to compensate for the phase-velocity mismatch induced by the transistor's intrinsic properties.