Provided are a display panel including a scan driver and a method of operating the same. The display panel includes a shift register including a plurality of stages that shifts and outputs a clock signal. A display area in the display panel is divided into a plurality of driving areas. The stages of the shift register corresponding to each driving area form a stage group. In each stage group, the stages included in the stage group sequentially output a scan signal by using an independent start signal.

A display panel includes a shift register and an active terminator. The shift register has a drive circuit coupled to one end of a gate line. The active terminator is coupled to the other end of the gate line and includes a first transistor, a second transistor, and a first capacitor. The first transistor has a first terminal connected to a first clock signal, a second terminal connected to the gate line, and a third terminal. The second transistor has a first terminal connected to a first internal node, a second terminal connected to the third terminal of the first transistor, and a third terminal connected to a first DC voltage source. The first capacitor has a first terminal connected to the gate line and a second terminal connected to the third terminal of the first transistor and the second terminal of second transistor.

The present disclosure discloses a detection circuit of a gate driver, an array substrate, a display device and a detection method thereof. Gate scanning signals of each of the signal output ends are derived to a detection signal line through signal deriving circuits, such that the gate scanning signals are transmitted to a discrimination circuit outside the array substrate. The discrimination circuit can acquire in real time and record the gate scanning signals, so as to detect the gate scanning signals in real time, and further rapidly diagnose whether the gate scanning signals are abnormal based on detection results, and rapidly locate the positions at which the gate scanning signals are abnormal, so as to timely troubleshoot the fault.

A shift register circuit and its driving method, a display panel, and a display device are provided. The shift register circuit includes an input module, a first inverter, a second inverter, and an output module. The input module is connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, to respond to signals from the second and third input terminal and control a voltage of a first node. In the first inverter, an input terminal is connected to the first node, and an output terminal is connected to a second node. In the second inverter, an input terminal is connected to the second node, and an output terminal is connected to the first node. The output module provides a signal of the fourth input terminal to an output terminal of the output module, and also provides a voltage of a first power terminal to the output terminal of the output module.

A First In First Out (FIFO) memory includes storage units. Outputs of the storage units are connected to one node. The storage unit includes storage sub-units, a selector, and a drive. An input of the selector is connected to outputs of the storage sub-units. An input of the drive is connected to an output of the selector. Driven by a first pointer signal, the storage sub-units receive storage data. Driven by a second pointer signal, the drive outputs the storage data.

A display device includes: a plurality of gate lines; and a gate driver including a plurality of stages which transmits a gate voltage to the gate lines, where first to fourth clock signals and first to fourth inverted clock signals having phases opposite to phases of the first to fourth clock signals, respectively, are sequentially input to each repetition unit of the stages, where each repetition unit is defined by eight consecutive stages, a carry signal output by a j-th stage is transmitted to a (j+4)th stage, and a carry signal output by the (j+4)th stage is transmitted to the j-th stage, where j is a natural number.

There is disclosed a shift register, a gate integrated driving circuit and a display screen. In the shift register, a connection point between the source of the first thin film transistor (T1) and the drain of the second thin film transistor (T2) is set as the first pulling-up node (PU1), a connection point between the capacitor (C1) and the gate of the third thin film transistor (T3) is set as the second pulling-up node (PU2), and the leakage-proof module is added between the first pulling-up node (PU1) and the second pulling-up node (PU2). The leakage-proof module is configured to, under the control of the display control signal terminal (CTI): conduct the path between the first pulling-up node (PU1) and the second pulling-up node (PU2) during the display period in a frame, so that the shift register can output a normal gate-on signal; and disconnect the path between the first pulling-up node (PU1) and the second pulling-up node (PU2) during the touch period in the frame, which is equivalent to connecting a resistor having a large resistance in a discharging path of the capacitor (C1) in series, so that the discharging of the capacitor (C1) can be slowed greatly, and a leakage speed of the capacitor (C1) is decreased effectively, which avoids a problem of abnormal displaying occurs possibly in an application of a touch screen with a high reporting rate.

There is disclosed a shift register unit, a gate driving circuit and a display device. The shift register unit includes a shift register module configured to delay a phase of a signal from the input terminal, and output the delayed signal at the first output terminal; a first input module configured to set the first node to be at a second voltage level; a second input module configured to set the first node to be at the first voltage level, and apply the signal from the input terminal to the first node; and an output module configured to set the second output terminal to be at the second voltage level when the first output terminal is at the first voltage level, and set the second output terminal to be at the first voltage level when the first node is at the first voltage level.

The present disclosure describes a shift register unit, an organic light-emitting display panel and a driving method. The shift register unit comprises a node potential controller and an output unit. The node potential controller comprises a first output end and a second output end. The output unit is configured to output, based on a first control signal from the first output end and a second control signal from the second output end, a first level signal or a second level signal. According to the solutions provided by the application, the potential of each node in the shift register unit is stable and controllable, and contributed to the avoidance of output logic execution problem in the shift register unit caused by unstable node potential when each control signal level of the shift register unit jumps.

A shift register is provided, which includes a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit. The blanking input circuit may provide a blanking input signal to a first control node according to a second clock signal. The blanking control circuit may provide a first clock signal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node. The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to the first clock signal. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.