The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).

The present invention relates to a processing of a signal under test in order to compensate frequency variations in the signal under test. For this purpose, the signal under test is mixed with a further digital signal. A frequency of the further signal which is used for mixing with the signal under test may be adapted in real-time according to frequency variations in the signal under test.

A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the last passing point, write data within the logic circuit of the tester identifying the last passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.

A signal abnormality detection system and a method thereof are provided. The signal abnormality detection system includes a signal sensor and a computing device. The signal sensor generates a sample signal to be tested through sensing. The computing device is signal-connected to the signal sensor to receive the sample signal to be tested, perform a correction on the sample signal to be tested, and perform a time-frequency transform on a one-dimensional signal generated after the correction to generate a two-dimensional time-frequency signal. The computing device reconstructs the two-dimensional time-frequency signal by using an abnormality detection model to calculate a reconstructed difference value. The computing device performs comparison to determine whether the reconstructed difference value is greater than a detection threshold to determine whether the sample signal to be tested is an abnormal sample.

An electrical operating device includes measuring equipment for an electrical measured variable, and preprocessing equipment for digital measured values. The preprocessing equipment has an integrated circuit and an electronic memory component for configuring a logic circuit. A processor evaluates preprocessed measurement data and, on the basis of the evaluation, transmits data telegrams to other electrical operating devices. The preprocessing equipment calculates a respective checksum for a digital measured value, and the processor recognizes a malfunction from the measured value and the checksum of the measured value, and suppresses the evaluation and/or the transmission of the data telegrams in the event of a malfunction. There is also described a method for recognizing malfunctions.

An example test system includes a circuit to sample a signal that is repetitive in cycles to obtain data; a processor configured to generate an eye diagram based on the data, where the eye diagram represents parametric information about the signal; and a functional test circuit to receive the signal and to perform one or more functional tests on the signal. The test systems is configured to receive the signal from a unit under test and to allow the signal to pass to the functional test circuit inline without changing at least part of the signal.

A signal analyzer for analyzing a signal includes a frontend with at least two interleaved digitizers configured to digitize an input signal, thereby generating a digitized input signal. The signal analyzer also includes a first interleave alignment filter established by a hardware interleave alignment filter that is configured to hardware-compensate non-ideal effects of the frontend in the digitized input signal in real-time, thereby generating a hardware-compensated, digitized input signal. Further, the signal analyzer includes an acquisition memory configured to store the hardware-compensated, digitized input signal, thereby acquiring an acquired signal. Moreover, the signal analyzer includes a second interleave alignment filter configured to fine-compensate further non-ideal effects of the frontend in a post-processing of the acquired signal.

A method for testing crosstalk effect includes: obtaining a test signal and an interference input signal; inputting the test signal into a crosstalk effect test circuit obtained by simulation, so as to obtain an interfered signal; and when a rise time of the interfered signal or a fall time of the interfered signal is greater than a preset time threshold, determining that an excessive crosstalk effect exists in an integrated circuit under test. The crosstalk effect test circuit includes a first circuit, N second circuits, and N capacitors. The first circuit is configured to simulate an interfered first signal circuit in the integrated circuit under test; the N second circuits are configured to simulate N second signal circuits that interfere with the first signal circuit in the integrated circuit under test.

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.