An optical circuit module in which an optical fiber array and an optical circuit substrate are connected, the optical fiber array including a groove substrate in which a groove for optical fiber alignment is formed, a pressing plate stacked on and bonded to the groove substrate, and an optical fiber bonded to and fixed in the groove of the groove substrate, and the optical circuit substrate including an input/output waveguide. In a connection surface of the optical circuit module, an area of a common portion in a cross section of the optical circuit substrate and the pressing plate is larger than an area of a common portion in a cross section of the optical circuit substrate and the groove substrate.

A photonic integrated circuit (PIC) package comprising a first die, the first die comprising a first optical waveguide and a first trench extending from a first edge of the first die to the first optical waveguide. The first trench is aligned with the first optical waveguide. A second die comprises a second optical waveguide and a second trench extending from a second edge of the second die to the second optical waveguide. The second trench is aligned with the second optical waveguide. An optical wire comprising an uncladded glass fiber comprises a first terminal portion extending within the first trench and a second terminal portion extending within the second trench. The first terminal portion is aligned with the first optical waveguide and the second terminal portion is aligned with the second optical waveguide.

A method of assembling an optical device including: providing a photonic integrated circuit including a plurality of vertical-coupling elements disposed along a main surface of the photonic integrated circuit; attaching an optical subassembly to the photonic integrated circuit; removably connecting a fiber connector to a ferrule frame, in which the fiber connector is attached to an array of optical fibers; aligning the ferrule frame to the optical subassembly using an active alignment process; and securely connecting the ferrule frame to the optical subassembly after the active alignment process.

Various embodiments provide for computational systems including multiple circuit packages, each circuit package comprising an electronic integrated circuit having multiple processing elements and intra-chip bidirectional photonic channels connecting the processing elements into an electro-photonic network, with inter-chip bidirectional photonic channels connecting the processing elements across the electro-photonic networks of the multiple circuit packages into a larger electro-photonic network.

An optical assembly includes stacked planar lightwave circuit (PLC) members each having a plurality of waveguides in a respective plane, to provide optical connections to two-dimensional arrays of external optical waveguides (e.g., optical fiber cores), with one array including non-coplanar groups of waveguides having group members that are alternately arranged in a lateral direction. An optical assembly may provide optical connections between array of cores having a different pitch and/or orientation to serve as a fanout interface. Methods for fabricating an optical assembly are further provided.

Optical beam forming at the inputs/outputs of a photonic chip and to the spectral broadening of the light coupled to the chip. The photonic chip comprises an optical waveguide layer supported on a substrate. The chip includes an optical waveguide structure made of silicon and a coupling surface grating. The photonic chip has a front face on the side facing the coupling surface grating and a rear face on the side facing the substrate. A reflecting collimation structure is integrated in the rear face to modify the mode size of an incident light beam. The coupling surface grating is designed to receive light from the optical waveguide structure and to form a light beam directed to the reflecting collimation structure. The invention further relates to the method for producing such a chip.

Structures for a photonics chip, testing methods for a photonics chip, and methods of forming a structure for a photonics chip. A photonics chip includes a first waveguide, a second waveguide, an optical tap coupling the first waveguide to the second waveguide, and a photodetector coupled to the second waveguide. A laser is attached to the photonics chip. The laser is configured to generate laser light directed by the first waveguide to the optical tap.

A process for delaying a useful optical signal (P1) having a wavelength value λ between 0.2 μm and 3 μm, with respect to a reference optical signal (P2) having the same wavelength value λ. The process includes having the useful optical signal propagate along a tapered fiber portion. A length of the tapered fiber portion can be varied using stretching means that are light, less cumbersome and less expensive compared to those necessary for a standard optical fiber. In addition, the delay value which is effective for the useful optical signal can be varied over a wide range. Such process can be useful for interferometry measurements in particular.

An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.