Aspects of the present disclosure describe a method including predicting a first set of ansatz terms and a first plurality of amplitudes associated with the first set of ansatz terms; minimizing energy of the system based on the first set of ansatz terms and the first plurality of amplitudes; computing perturbative corrections using one or more ansatz wavefunctions; determining whether energy of the system converges; and predicting, in response to determining that the energy of the system does not converge, a second set of ansatz terms and a second plurality of amplitudes associated with the second set of ansatz terms.

A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.

Various embodiments comprise systems, methods, mechanisms, apparatus, and improvements thereof providing a machine learning based inverse design method for mm-wave/RF power amplifiers (PAs). Methods according to embodiments provide for efficiently synthesizing power amplifier matching circuit (output matching/output power combiner/backoff efficient output power combiner, interstage matching and input matching/input power divider and phase shifter) for a close to optimum solution in terms of matching bandwidth, efficiency and load modulation, which can exceed the performance limitations of traditional matching network designs.

A method for reducing influence of a remote reference power noise on signal quality is provided. A remote reference power plane connected to a power module is identified according to a schematic diagram of signal design, and a noised power plane is determined. A position of the noised power plane is found in a PCB, and whether the noised power plane is remote referenced by a high-speed signal is judged. Placement positions and number of connection capacitors are determined according to a layout and routing position of the high-speed signal and a width of the noised power plane. Two capacitors with fixed capacitance values are placed at the placement positions of the connection capacitors. Connection capacitors are added to a position of a noised remote reference power plane of a signal line for connecting the power plane and the ground.

A method for recognizing various analog circuit structures is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a feature extraction of a training circuit to extract all sub-circuits for generating multiple training samples; classifying multiple training samples by a classifier to obtain classified building blocks; performing a feature extraction of each schematic of a target circuit to convert as a feature graph and encoding feature graph as a feature matrix; classifying feature matrix by the classifier to generate multiple groups of classified devices; and clustering multiple groups of classified devices to acquire identified sub-circuits.

A method for recognizing various analog circuit structures is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a feature extraction of a training circuit to extract all sub-circuits for generating multiple training samples; classifying multiple training samples by a classifier to obtain classified building blocks; performing a feature extraction of each schematic of a target circuit to convert as a feature graph and encoding feature graph as a feature matrix; classifying feature matrix by the classifier to generate multiple groups of classified devices; and clustering multiple groups of classified devices to acquire identified sub-circuits.

An embodiment discloses an apparatus for controlling a camera module, including a parameter generation unit configured to generate a parameter entity group, calculate a fitness value of the parameter entity group based on a step response characteristic of an output signal, and generate an offspring entity by applying weight-gain elitism to a parameter entity having the smallest fitness value among parameter entities included in the parameter entity group, and a controller configured to generate a control signal by multiplying an error signal by a parameter.

An embodiment discloses an apparatus for controlling a camera module, including a parameter generation unit configured to generate a parameter entity group, calculate a fitness value of the parameter entity group based on a step response characteristic of an output signal, and generate an offspring entity by applying weight-gain elitism to a parameter entity having the smallest fitness value among parameter entities included in the parameter entity group, and a controller configured to generate a control signal by multiplying an error signal by a parameter.

A method for determining electrical parameter values of the transistors of an analog circuit of a system on chip includes breaking the circuit down into a set of blocks connected to one another; establishing the wiring diagram of said circuit; defining a set of electrical constraints that are specific to said circuit, blocks and transistors of each block; defining electrical parameters of the circuit, block and transistors; selecting for each transistor of the circuit an operator for calculating the electrical parameter values of said transistor; generating structured diagrams of each block of the circuit from the defined constraints and the chosen operators; assembling said structured diagrams of blocks into a general diagram of the circuit; identifying whether there is any conflict; and, if so, emitting an alarm signal.

The present disclosure provides a method for improving the computational efficiency of an electromagnetic transients program (EMTP-type) phase domain synchronous machine model. The method comprises: acquiring a traditional phase domain synchronous machine model; acquiring matrix relations between mutual inductance matrices of stator windings and rotor windings according to a trigonometric transformation equation; substituting the matrix relations into the original expression of R.sub.eq and the original formulation of e.sub.h(t), respectively, and deriving to obtain a simplified formulation of the equivalent resistance matrix R.sub.eq and a simplified formulation of the total history term e.sub.h(t); and acquiring an efficient phase domain synchronous machine model. According to the embodiment of the disclosure, in the provided model, the equivalent resistance matrix of the phase domain synchronous machine model and the matrix used in the calculation of the history term are converted into constant sparse matrices, thereby improving the calculation efficiency of the model.