Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.

The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation.

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.

According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.

A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.

A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

A semiconductor device includes a cell region and a peripheral circuit region. The cell region includes gate electrode layers stacked on a substrate, channel structures extending in a first direction, extending through the gate electrode layers, and connected to the substrate, and bit lines extending in a second direction and connected to the channel structures above the gate electrode layers. The peripheral circuit region includes page buffers connected to the bit lines. Each page buffer includes a first and second elements adjacent to each other in the second direction and sharing a common active region between a first gate structure of the first element and a second gate structure of the second element in the second direction. Boundaries of the common active region include an oblique boundary extending in an oblique direction forming an angle between 0 and 90 degrees with the second direction.