A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.

A neuromorphic device may include: pre-synaptic neurons; row lines extending in a first direction from the pre-synaptic neurons, respectively; post-synaptic neurons; column lines extending in a second direction from the post-synaptic neurons, respectively, the second direction crossing the first direction; and synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values. The synapses may be programmed with at least one pattern based on the various fixed resistance values.

The present invention discloses a multi-bit-per-cell three-dimensional read-only memory (3D-OTP.sub.MB). It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.

The present invention discloses a three-dimensional vertical read-only memory (3D-OTP.sub.V). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming.

A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.

An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.

The present disclosure provides a fuse storage cell. The fuse storage cell includes a transistor and N fuse elements. The transistor includes a source, a drain, and a gate. Each fuse element of the N fuse elements includes a first terminal and a second terminal. The first terminal of the fuse element is electrically connected to the drain of the transistor, and the second terminal of the fuse is configured for inputting a read voltage or a programming voltage. N is a positive integer.

A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.

An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided. In one form, an eFuse memory cell includes: a programming transistor, where a source of the programming transistor is grounded; a first electric fuse having a first terminal and a second terminal opposite to the first terminal, where the first terminal is connected to a drain of the programming transistor; one or more second electric fuses connected in parallel to each other, where each of the second electric fuses is connected in parallel with the first electric fuse, the second electric fuse has a third terminal and a fourth terminal opposite to the third terminal, and the third terminal is connected to the drain of the programming transistor; a word line connected to a gate of the programming transistor; a first programming bit line connected to the second terminal of the first electric fuse; and one or more second programming bit lines in a one-to-one correspondence with the second electric fuses, the second programming bit line being connected to the fourth terminal of the corresponding second electric fuse. The eFuse memory cell provided in the present disclosure has an opportunity to be programmed at least twice, thereby improving a yield rate of the eFuse memory array.