A data relay device including: a storage circuit that stores, for each of storages, an upper limit number indicating a number of input/output (I/O) commands that are transmittable; a relay circuit that relays data transmitted and received between one or more control devices and the storages; and a control circuit that performs: counting, for each storage, a number of commands indicating a number of the I/O commands that have been transmitted via the relay circuit and for which no response has been returned from transmission destination storages among the storages; in response to a request to retry transmission of the I/O commands from one storage among the storages, registering a first number in the storage circuit as the upper limit number of commands that corresponds to the one storage, the first number being a number obtained by subtracting one from a counted value of the number of commands.

Disclosed is a memory device including a plurality of memory banks, each of which performs an operation based on first operand data including pieces of first unit data and second operand data including pieces of second unit data and a processing in-memory interface unit (PIM IU) that delivers signals for an operation request to the plurality of memory banks. Each of the plurality of memory banks includes a memory cell array configured to store one of the pieces of first unit data and a PIM engine that reads the one of the pieces of first unit data from the memory cell array, reads the pieces of second unit data broadcast to the plurality of memory banks, and generates an operation result by performing an operation based on the one of the pieces of first unit data and the pieces of second unit data.

A system and method for exposing volumes with underlying read-write mediums to user operations. When a medium is in the process of being migrated to a storage array, a volume which relies on the medium can be exposed to user operations (e.g., snapshots, read and write operations) once the portions of the medium which underlie the volume have been migrated. The volume can be exposed to user operations while one or more other portions of the medium are unfilled and while the medium is in an intermediate read-write state.

Managing input/output (‘I/O’) queues in a data storage system, including: receiving, by a host that is coupled to a plurality of storage devices via a storage network, a plurality of I/O operations to be serviced by a target storage device; determining, for each of a plurality of paths between the host and the target storage device, a data transfer maximum associated with the path; determining, for one or more of the plurality of paths, a cumulative amount of data to be transferred by I/O operations pending on the path; and selecting a target path for transmitting one or more of the plurality of I/O operations to the target storage device in dependence upon the cumulative amount of data to be transferred by I/O operations pending on the path and the data transfer maximum associated with the path.

An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Methods, systems, and devices for dynamically tuning host performance booster thresholds are described. A memory system may include a set of memory devices and an interface configured to communicate commands with a host system coupled with the memory system. The interface may communicate commands to the memory system according to a first command mode associated with a logical address space including a plurality of regions and communicate commands according to a second command mode associated with physical memory address. The memory system may further include a controller that may determine a region activated for the second command mode, receive a first plurality of commands, determine, upon deactivating the region, a first threshold based on a first quantity of read commands serviced according to the second command mode. The controller may activate the region for the second command based on a second quantity of read commands received exceeding the first threshold.

Aspects include obtaining data to be transformed. A selected transformation to be applied to the data is determined based on a storage block address list entry (SBALE) in a storage block address list (SBAL). The SBALE includes at least one field that is used in determining the selected transformation to be applied. The selected transformation is applied on the data to generate transformed data and the transformed data is placed in a location specified by the SBAL.

A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.

Storage devices can be configured to desirably reduce the number of times a zone reset or erasure occur via the use of one or more paired overwrite memory blocks. These storage devices can include a plurality of memory devices with some of these memory devices designated as overwrite memory devices. A controller within the storage device can be configured to direct the storage device to generate one or more subsets within the memory devices such as zones, pair each of subsets with at least one or more overwrite memory devices, store data sequentially within the subset of memory devices, and store any received overwrite data in the overwrite memory devices in chronological order. Data stored within the subsets of memory devices are not erased and instead of being overwritten directly, are instead pointed via a control table to a location in the overwrite memory devices storing the corresponding overwrite data.

A memory control method and a memory storage system are provided. The method includes: in a memory closing procedure, sending, by a host system, a first control command to a memory storage device which includes a volatile memory module and a rewritable non-volatile memory module; closing, by the memory storage device, the volatile memory module in response to the first control command; and in a state where the volatile memory module is closed, maintaining, by the memory storage device, the rewritable non-volatile memory module to be operated normally.