A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed.

A method of operating a nonvolatile memory system including a memory device having a plurality of memory blocks includes selecting a source block among the plurality of memory blocks in the nonvolatile memory system, and performing a reclaim operation for the source block based on the number of program and erase cycles which have been performed on the source block.

Provided are a computer program product, system, and method for selective write control in accordance with the present description. In one aspect, a write operation which is associated with a read operation, may be selectively discarded if write operations have been disabled and if the write operation is directed to update a designated write operation acceptance area such as metadata associated with the target data set, for example. As a result, the read operation may be permitted to proceed and will not fail because the associated write operation was discarded rather than attempting to commit the write operation to the designated write operation acceptance area, thereby avoiding an error condition for a storage unit such as a volume, in which write operations have been disabled. Accordingly, applications which seek to perform read operations may be permitted to access data stored on such a volume. Other aspects are described.

A memory controller controls a memory device including memory blocks, and can equalize wear levels of cores for controlling memory devices. The memory controller includes: cores for controlling the zones; a reset information controller for generating reset count values representing a number of reset requests input with respect to the zones, in response to a reset request, and generating reset count sum values obtained by summing reset count values of zones controlled by each of the cores; and a wear level manager for controlling the cores such that a core that is different from a first core having a highest reset count sum value from among the cores controls some of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.

A memory system includes: a memory device including a plurality of memory blocks configured to store data; and a controller configured to determine a power level for an operation corresponding to a command received from a host, and provide the determined power level to a memory block which is subject to the operation.

Described are a system, method, and computer program product for generating a data storage server distribution pattern. The method includes determining a set of servers and raw data to be stored. The method also includes transforming the raw data according to an error-correcting code scheme to produce distributable data. The method further includes determining a server reliability of each server in the set of servers. The method further includes generating the data storage server distribution pattern based on maximizing a system reliability relative to maximizing a system entropy. System reliability may be based on a minimum reliability of the set of servers, and system entropy may be based on a cumulated information entropy of each server of the set of servers. The method further includes distributing the distributable data to be stored across at least two servers of the set of servers according to the data storage server distribution pattern.

Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.

Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

A computing system includes: a storage device, coupled to central processing unit, includes: an in-storage processing engine configured to receive and manage application data from an application executed in a host computer, an in-storage processing coordinator, in the in-storage processing engine, configured to perform in-storage processing with formatted data, based on the application data, includes performing integer math operations, floating point math operations, Boolean operations, reorganization of data bits or symbols, and combinations thereof on the application data, and a data preprocessor, in the in-storage processing coordinator, configured to align the formatted data from the application data to return an in-storage processing output to the application for continued execution.