According to one embodiment, a memory system includes a volatile memory, a power supply circuit, and a controller. The power supply circuit includes a first power supply path in which power supplied from a host device is supplied to the volatile memory, a second power supply path in which the power is supplied from the internal power supply to the volatile memory, and a switching device that switches between the first power supply path and the second power supply path. In response to an instruction for a transition to a low power consumption mode received from the host device, the controller outputs, to the switching device, an instruction to switch the power supply circuit from the first power supply path to the second power supply path.

According to some examples, systems and methods are provided for determining a set of power states supported by a data storage device and applying an operation to the data storage device based on whether the set of power states includes a low power state.

An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.

A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.

Systems, methods and apparatuses to control power usage of a data storage device. For example, the data storage device has a temperature sensor configured to measure the temperature of the data storage device are provided. A controller of the data storage device determines a set of operating parameters that identify an operating condition of the data storage device. An inference engine of the data storage device determines, using an artificial neural network in the data storage device and based on the set of operating parameters, an operation schedule for a period of time of processing input and output of the data storage device. The operation schedule is configured to optimize a performance of the data storage device in the period of time without the temperature of the data storage device going above a threshold.

A memory system includes: a memory device including a plurality of memory blocks configured to store data; and a controller configured to determine a power level for an operation corresponding to a command received from a host, and provide the determined power level to a memory block which is subject to the operation.

A storage system includes a first storage apparatus including a first storage portion and a second storage portion, a second storage apparatus including a third storage portion and a fourth storage portion, and a storage management apparatus including a processor configured to control the first storage apparatus in an active state and control the second storage apparatus in a standby state, cause the first storage apparatus to execute first data relocation processing, cause the second storage apparatus to execute second data relocation processing, cause the first storage apparatus to suspend the first data relocation processing and cause the second storage apparatus to continue the second data relocation processing, switch the first storage apparatus from the active state to the standby state and switch the second storage apparatus from the standby state to the active state, and cause the first storage apparatus to resume the first data relocation processing.

A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

A data backup method of a storage device which includes a storage controller, a buffer memory, and a plurality of nonvolatile memory devices, the method including: detecting a power-off event of an external power provided to the storage device; deactivating a host interface of the storage controller in response to the detection of the power-off event: moving data stored in the buffer memory to a static random access memory (SRAM) in the storage controller; blocking or deactivating a power of the buffer memory; setting an interleaving mode of the plurality of nonvolatile memory devices to a minimum power mode; and programming the data moved to the SRAM to at least one of the plurality of nonvolatile memory devices.