G06F3/0625

Apparatuses and methods to mask write operations for a mode of operation using ECC circuitry
11544010 · 2023-01-03 · ·

An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.

MEMORY DEVICE HAVING A PLURALITY OF LOW POWER STATES

A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

COMPUTER SYSTEM FOR FACILITATING FINANCIAL TRANSACTIONS AND REDUCING FRAUD
20220413728 · 2022-12-29 · ·

A systems and method for reconfigurable and/or updatable lightweight electronic devices are disclosed for a computer system for facilitating financial transactions and reducing the opportunity for fraud. Via use of such a device, system, or method, various capabilities for a user are provided, simplified, secured, and/or made more convenient. The system may interact with various other devices or systems, including those that are cloud-based or communicate through the cloud, and may utilize various local sensors, in order to provide one or more of improved access, monitoring, user diagnostics, and so forth.

MAINTAINING QUEUES FOR MEMORY SUB-SYSTEMS
20220413719 · 2022-12-29 ·

Methods, systems, and devices for data stream processing for maintaining queues for memory sub-systems are described. A number of commands included in a queue of a plurality of queues of a memory die of a memory sub-system can be determined. Each queue can be associated with a respective priority level and can be configured to maintain a respective set of commands. A command can be assigned to the queue based on a number of commands included in the queue. One or more commands can be issued from the queues based on the respective priority levels of the queues.

Power Limits for Virtual Partitions in a Processor

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

PRECISE POWER CYCLE MANAGEMENT IN DATA STORAGE DEVICES
20220413583 · 2022-12-29 ·

Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

Technologies for providing advanced management of power usage limits in a disaggregated architecture

Technologies for providing advanced management of power usage limits in a disaggregated architecture include a compute device. The compute device includes circuitry configured to execute operations associated with a workload in a disaggregated system. The circuitry is also configured to determine whether a present power usage of the compute device is within a predefined range of a power usage limit assigned to the compute device. Additionally, the circuitry is configured to send, to a device in the disaggregated system and in response to a determination that the present power usage of the present compute device is not within the predefined range of the power usage limit assigned to the present compute device, offer data indicative of an offer to reduce the power usage limit assigned to the present compute device to enable a second power utilization limit of another compute device in the disaggregated system to be increased.

BALANCING POWER, ENDURANCE AND LATENCY IN A FERROELECTRIC MEMORY

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

PROGRAMMING MEMORY CELLS WITH CONCURRENT REDUNDANT STORAGE OF DATA FOR POWER LOSS PROTECTION

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

Distributed storage system for long term data storage
11531495 · 2022-12-20 ·

A distributed storage system for the long-term storage of data objects that is implemented utilizing one or more distinct storage sites that may be comprised of system controllers and object storage systems that act in concert to embody a single distributed storage system. A system may include a one or more types and/or instances of object storage systems. A system may include object storage systems that are powered on for a limited time as required to complete queued data operations. A system may further include system controllers associated with logical and/or physical sites that coordinate object, user, device, and system management functionally.