A memory system includes a nonvolatile memory, and a memory controller configured to control the nonvolatile memory. The nonvolatile memory stores a busy table. The memory controller loads the busy table and controls a chip enable signal for the nonvolatile memory based on the busy table.

A data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive information from a host about which area, if any, in a host memory buffer will be powered on during a low-power state; and in response to the information indicating that a first area of the host memory buffer will be powered on during the low-power state, flush data from a second area of the host memory buffer that will not be powered on during the low-power state to the first area of the host memory buffer prior to entering the low-power state. Other embodiments are provided.

According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

It is desired to provide a technique capable of reducing the time and the power consumption required for computation. Provided is an information processing apparatus including a storage control unit that writes data read from a read target area of an external memory having multiple dimensions to a storage area having the multiple dimensions and a processing unit that executes processing based on the data of the storage area, in which the storage control unit moves the read target area in a first dimension direction in the external memory and performs first overwrite of a back end area of the storage area in a direction corresponding to the first dimension direction with data of a front end area of the read target area after movement in the first dimension direction.

An image forming apparatus includes a solid state drive (SSD) that stores information, a Serial Advanced Technology Attachment (SATA) controller that reads information from the SSD, writes information to the SSD, and transmits a device sleep (DEVSLP) signal for shifting the SSD to a DEVSLP state, and a power source control unit that can stop power to the SATA controller and transmits the DEVSLP signal for shifting the SSD to the DEVSLP state during a period in which the power to the SATA controller is stopped.

Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.

In certain aspects, a memory system may include at least one memory device and a memory controller coupled to the at least one memory device. Each memory device may include an array of memory cells and a control logic coupled to the array of memory cells. The memory controller and the control logic of the memory device may be powered by a first power source having a first predetermined power consumption threshold. The array of memory cells of the memory device may be powered by a second power source having a second predetermined power consumption threshold. The memory controller may be configured to maintain a first queue of memory operations, wherein execution of the memory operations in the first queue causes power consumption from the first power source; maintain a second queue of memory operations, wherein execution of the memory operations in the second queue causes power consumption from the second power source; separately determine whether execution of subsequent memory operations in the first and second queues, respectively, would cause the corresponding first and second power sources to be overloaded; execute, based on the determination, the subsequent memory operation in the first or second queue that would not cause the corresponding first or second power source to be overloaded; and delay, based on the determination, the subsequent memory operation in the first or second queue that would cause the corresponding first or second power source to be overloaded.

Described is a process measurement device having an interface for connecting a plug-in memory, in which a processing measurement device includes a memory operating device that can switch the process measurement device into a memory access mode when the memory is connected to the process measurement device. Also described is a power supply that ensures that the energy demand required for read access or write access to the process measurement device is automatically covered after the connection of the memory by increasing the amount of electrical energy that is freely available in the process measurement device. Undesired undersupply of the process measurement device can thereby be effectively avoided.