Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory. In one aspect, a memory controller accumulates secondary parity for the user data in a first portion of the parity buffer while a second portion of the parity buffer is still being used to store the primary parity. The memory controller may compute the secondary parity from present content of the first portion of the parity buffer and primary parity presently stored in the second portion of the buffer.

A Key-Value (KV) storage device is disclosed. The KV storage device may include storage for objects, each object including data associated with a key. A host interface layer may receive requests to read data associated with a key from the storage, to write data associated with a key to the storage, and a boot request to get boot data from the storage. A boot request processor may process the boot request using the storage.

An operation method of a storage device, which includes a nonvolatile memory device, includes receiving a first key-value (KV) command including a first key from an external host device; transmitting a first value corresponding to the first key from the nonvolatile memory device to the external host device as first user data, in response to the first KV command; receiving a second KV command including a second key, from the external host device; and performing a first administrative operation based on a second value corresponding to the second key, in response to the second KV command. The first KV command and the second KV command are KV commands of a same type.

A system and method employing a distributed hardware architecture, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations are disclosed. A compute node may be implemented independent of a host compute system to manage and to execute data processing operations. Additionally, an unique algorithm architecture and processing system and method are also disclosed. Different types of nodes may be implemented, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations.

A data processing method for a network adapter includes the network adapter that obtains a first input/output (I/O) command. The first I/O command instructs to write data stored in a local server to at least one remote server, and the first I/O command includes address information and length information that are of the data and that are stored in the local server. The network adapter splits the data based on the address information and the length information to obtain a plurality of groups of address information and length information. The network adapter obtains, from the local server based on the groups of address information and length information, data corresponding to the groups of address information and length information, and sends the data to the at least one remote server.

The present disclosure generally relates to host memory buffer (HMB) cache management. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

A memory such as a volatile memory device capable of having a reduced area is provided. The volatile memory device comprises a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier, a first normal mat disposed between the first sense amplifier and the second sense amplifier, and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, and a first reference mat disposed on the first normal mat between the first sense amplifier and the second sense amplifier, and including a first complementary bit line connected to the first sense amplifier and a second complementary bit line connected to the second sense amplifier.

In a running distributed data storage system that actively processes I/Os, metadata nodes are commissioned and decommissioned without taking down the storage system and without introducing interruptions to metadata or payload data I/O. The inflow of reads and writes continues without interruption even while new metadata nodes are in the process of being added and/or removed and the strong consistency of the system is guaranteed. Commissioning and decommissioning nodes within the running system enables streamlined replacement of permanently failed nodes and advantageously enables the system to adapt elastically to workload changes. An illustrative distributed barrier logic (the “view change barrier”) controls a multi-state process that controls a coordinated step-wise progression of the metadata nodes from an old view to a new normal. Rules for I/O handling govern each state until the state machine loop has been traversed and the system reaches its new normal.

A storage device includes a nonvolatile memory device and a storage controller. The nonvolatile memory device includes a first memory region having a first write speed and a second memory region having a second write speed different from the first write speed. The storage controller includes an internal buffer and stores data from an external host in the first memory region by priority in a first mode. The storage controller controls a data migration operation by performing a read operation-transfer operation to read a second data that is pre-stored in the first memory region by a first unit and to transfer the first unit of data to a data input/output (I/O) circuit of the nonvolatile memory device a plurality of times and by storing the second data transferred to the data I/O circuit in the second memory region.

Systems and methods of reducing storage requirements for storing information defining a virtual space are presented herein. In particular, a compressed format of information defining a virtual space may be generated. The virtual space may include virtual space content modeled as polygons. An individual polygon may be defined by an individual set of vertices. The information defining the virtual space may include vertex position information, and/or other information. The vertex position information may comprise individual positions of individual vertices of individual polygons represented as vectors having vector components.