A system, computer program product, and computer-executable method for use with a distributed storage system comprising a plurality of storage nodes each having attached storage devices, the system, computer program product, and computer-executable method including receiving a request, at a first storage node of the plurality of storage nodes, to store a large portion of data, using at least one of a first type of data chunk and a plurality of a second type of data chunks to store the large portion of data, processing each of the plurality of the second type of data chunks, processing each of the at least one of the first type of data chunk, and returning an acknowledgement to the request.

A storage system includes data storage devices, bus conductors, and mobile reader/writer devices. Each of the storage devices is positioned between insulators, is at one of a plurality of locations on one of one or more shelf assemblies, and comprises a processor coupled to a memory and an interface device. One of the bus conductors is adjacent each of the insulators. Each of the reader/writer devices includes a transport apparatus, a processor and a memory. The transport apparatus is configured to move one of the reader/writer devices to one or more of the locations when engaged. The processor is coupled to the transport apparatus and the memory and is configured to execute machine executable code to: engage the transport apparatus to position one of the reader/writer devices to one of the locations in response to a received operation; couple power to one of the storage devices; and execute the operation.

A semiconductor system includes a controller and a semiconductor device. The controller generates command signals, a composite control signal, and data signals. The semiconductor device generates a first mode signal and a second mode signal according to the command signals. The semiconductor device includes a write control circuit suitable for receiving the composite control signal and the data signals to determine an execution/non-execution of a data masking operation and a data bus inversion (DBI) operation when a write operation or a masking write operation is performed according to the first and second mode signals.

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

An information processing system includes: an information processing apparatus; and a terminal apparatus, wherein the terminal apparatus includes a first processor configured to measure response times for respective volumes in the information processing apparatus, and the information processing apparatus includes a second processor configured to reduce a capacity of an allocated cache memory in accordance with the response times.

In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.

The present disclosure includes apparatuses, methods, and systems for validating data stored in memory using cryptographic hashes. An embodiment includes a memory, and circuitry configured to divide the memory into a plurality of segments, wherein each respective segment is associated with a different cryptographic hash, validate, during a powering of the memory, data stored in each respective one of a first number of the plurality of segments using the cryptographic hash associated with that respective segment, and validate, after the powering of the memory, data stored in a second number of the plurality of segments, data stored in each respective one of a second number of the plurality of segments using the cryptographic hash associated with that respective segment.

Provided is a hybrid network end system device for a network system with an end system unit and a switch. The switch here exhibits at least one first port of the switch and a second port of the switch for connection with the network system.

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

A method, computer program product, and computer system for extending, by a computing device, transaction log page-buffers for Non-Volatile Random Access Memory (NVRAM) onto a solid state drive (SSD). It may be determined whether a bandwidth limit of the NVRAM has reached a threshold bandwidth. An IO may be processed on one of the NVRAM and the SSD based upon, at least in part, whether the bandwidth limit of the NVRAM has reached the threshold bandwidth.