Patent classifications
G06F3/0626
SPI interface enhanced flash chip and chip packaging method
An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.
N-way merge technique for updating volume metadata in a storage I/O stack
A N-way merge technique efficiently updates metadata in accordance with a N-way merge operation managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. The metadata is embodied as mappings from logical block addresses (LBAs) of a logical unit (LUN) accessible by a host to durable extent keys, and is organized as a multi-level dense tree. The mappings are organized such that a higher level of the dense tree contains more recent mappings than a next lower level, i.e., the level immediately below. The N-way merge operation is an efficient (i.e., optimized) way of updating the volume metadata mappings of the dense tree by merging the mapping content of all three levels in a single iteration, as opposed to merging the content of the first level with the content of the second level in a first iteration of a two-way merge operation and then merging the results of the first iteration with the content of the third level in a second iteration of the operation.
Automatically Re-Routing Multi-Cloud Holochain Data Ingestion Based on Network Architecture Availability to Internet of Things (IoT) Devices
Aspects of the disclosure relate to automatically re-routing multi-cloud holochain data ingestion based on network architecture availability for internet of things (IoT) devices. A computing platform may request information that describes each cloud computing environment of a multi-cloud computing environment to identify the cloud computing environment that may store consumer data. The computing platform may compare the information that describes each cloud computing environment to an enterprise organization's preferences for selecting a cloud computing environment. The cloud computing platform may validate the consumer data and may encrypt the consumer data using public and private key pairs. The computing platform may transmit the encrypted consumer data to the cloud computing environment that satisfies the enterprise organization's preferences.
BIOS VARIABLES STORAGE
In one example in accordance with the present disclosure, an electronic device is described. The example electronic device includes a NAND flash device to store a static data component of a variable. The example electronic device also includes a NOR flash device to store a dynamic data component of the variable. The electronic device further includes a controller to write the static data component of the variable to the NAND flash device. This controller is also to write the dynamic data component of the variable to the NOR flash device.
User controlled data-in for lower and middle page in MLC-fine QLC memories
Aspects of a storage device including a memory and a controller are provided. The memory includes non-volatile memory and volatile memory. The controller may determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence. The controller may read the first data from the system-level memory location when the page data is available at the system-level memory location. Alternatively, the controller may read the first data from the non-volatile memory when the page data is not available at the system-level memory location. Thus, the controller may perform a first programming operation associated with the first programming stage using the first data, thereby improving memory programming performance of the storage device.
COMPUTER PROGRAM PRODUCT, METHOD, APPARATUS AND DATA STORAGE SYSTEM FOR MANAGING DEFRAGMENTATION IN FILE SYSTEMS
Aspects of managing defragmentation in a data storage system comprising one or more storage apparatuses and a file system server connected to the one or more storage apparatuses and to one or more host computers are described, comprising: providing free space allocation information; allocating, in response to receiving an update request to update data stored in one or more first storage units of a plurality of storage units, one or more second storage units of the plurality of storage units indicated to be free based on the provided free space allocation information for writing update data of the update request, controlling writing update data to the allocated one or more second storage units, and controlling swapping logical addresses associated with the one or more second storage units with respective logical addresses associated with the one or more first storage units.
MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM
A memory system includes: a memory device including a plurality of memory blocks; and a controller including a memory, the controller being suitable for: selecting a source memory block and a target memory block among the plurality of memory blocks; loading map segments of map data for the source memory block on the memory; determining valid pages, among a plurality of pages included in the source memory block, through the map segments; loading valid data stored in the valid pages on the memory; updating map data for the valid data; and storing the valid data and the updated map data in a plurality of pages included in the target memory block.
Data processing system performing neural network operations and operating method thereof
A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.
Method, device and computer program product for data writing
Techniques for data writing involve: determining an unavailable storage zone in multiple storage zones of a storage area, wherein each storage zone is used to store a zip header and compressed data corresponding to the zip header; acquiring a reference zip header for the unavailable storage zone, wherein the reference zip header includes metadata indicating a zone length of the unavailable storage zone; and generating consecutive write requests for the storage area based at least on target data to be written to the storage area and the reference zip header, so as to write the target data to available storage zones in the multiple storage zones. Accordingly, rewriting of data can be implemented by constructing large consecutive write requests, thus improving the write performance of the storage device.
ENHANCED FILESYSTEM SUPPORT FOR ZONE NAMESPACE MEMORY
A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.