An accelerator device may generate and submit descriptors to be processed by the accelerator device. Software executing on a processor may submit descriptors to the accelerator device to be processed in parallel.

Embodiments provide a thread classification method that represents stack traces in a compact form using classification signatures. Some embodiments can receive a stack trace that includes a sequence of stack frames. Some embodiments may generate, based on the sequence of stack frames, a trace signature that represents the set. Some embodiments may receive one or more subsequent stack traces. For each of the one or more subsequent stack traces, some embodiments may determine whether a subsequent trace signature has been generated to represent the sequence of stack frames included within the subsequent stack trace. If not, some embodiments may generate, based on the trace signature and other subsequent trace signatures that were generated based on the trace signature, the subsequent trace signature to represent the subsequent sequence of stack frames.

A method, computer program product, and computing system for generating one or more unique network addresses for one or more storage array enclosures of a storage system. The one or more unique network addresses may be advertised to one or more storage processors of the storage system. The one or more storage processors may be configured to communicate with a plurality of storage devices of the one or more storage array enclosures based upon, at least in part, the one or more unique network addresses of the one or more storage array enclosures.

Concurrent threads may be synchronized at the level of the memory words they access rather than at the level of the lock that protects the execution of critical sections. Each lock may be associated with an array of flags and each flag may indicate ownership of certain memory words. A pessimistic thread may set flags corresponding to memory words it is accessing in the critical section, while an optimistic thread may read the corresponding flag before any memory access to ensure that the flag is not set and that therefore the associated memory word is not being accessed by the other thread. Thus, optimistic threads that do not have conflicts with the pessimistic thread may not have to wait for the pessimistic thread to release the lock before proceeding.

A method for access control of resources in a distributed storage system using an API level model. An ownership object is created corresponding to a volume. The ownership object includes a string defining the owner of the resource. Access rights are given to collaborators or groups and stored as property list fields in the ownership object. Any requestor not listed as the owner, a collaborator, or part of a user group is denied access to the resource.

A hyperscale artificial intelligence and machine learning infrastructure includes a plurality of racks, where: at least one or more of the racks include one or more GPU servers; at least one or more of the racks include one or more storage systems; each of the racks include one or more switches coupled to at least one switch in another rack; and the one or more GPU servers are configured to execute one or more artificial intelligence or machine learning applications, wherein data stored within the one or more storage systems is used as input to the one or more artificial intelligence or machine learning applications.

A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

A storage control apparatus, includes a memory; and a processor coupled to the memory and configured to: receive management information for managing data stored in a first storage device, generate, for each processing unit of the data, restoration information for restoring the management information, add the data to the restoration information by processing the data based on the management information on a second storage device, store, in the first storage device, the added restoration information, and reconstruct the management information on the second storage device based on the added restoration information when detecting an abnormality occurrence on the receiving the management information.