Patent classifications
G06F3/0629
CONTROL MODULE AND CONTROL METHOD THEREOF FOR SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
The present disclosure provides a control module and a control method thereof for an SDRAM. The control module includes a register and a controller. The controller is configured to: select a first command, wherein the first command includes at least two first memory commands; execute one of the at least two first memory commands; store an un-executed memory command of the at least two first memory commands in a register and back the un-executed memory command up as at least one first back-up memory command; select a second command, wherein the first command and the second command are stored in different memory bank groups; and execute the second command.
OPERATION METHOD OF MEMORY CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE
Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.
Data Storage Method, Data Reading Method, Data Storage Apparatus, Data Reading Apparatus, Storage Device in Storage System, and System
A data storage method includes that a first device generates N check units for M data units, where M and N are both positive integers, and M+N=K. The first device stores the K units in K hard disk modules in the storage system, where the K units include the M data units and the N check units. Each of the K hard disk modules stores one of the K units. Each hard disk module includes an interface module and a hard disk, and the interface module communicates with the hard disk.
DATA STORAGE DEVICE REDEPLOYMENT
Systems and methods are disclosed for data storage redeployment. For example, a controller of a data storage array can implement a process to determine when, or if, to redeploy a data storage device from a first data storage usage or tier having a first performance requirement to a second data storage usage or tier having a second performance requirement. In some embodiments, the first data storage tier performance requirement is for hot-data storage, and the second data storage tier performance requirement is for cold-data storage. Various criterion (e.g., a data storage device performance metric) threshold, such as a workload (e.g., LBAs written, LBAs read, or both) of the data storage device or bit error rate (BER), may be utilized in a redeployment determination.
SYSTEM TO ENHANCE MEMORY PROTECTION ASSOCIATED WITH KERNEL OF OPERATING SYSTEM
A computing system includes a processor, and the processor is arranged to execute: a guest virtual machine (VM), a hypervisor, and a primary VM, wherein an operating system (OS) runs on the guest VM, and an application (APP) runs on the OS. The kernel of the OS includes a protection service module and a memory management unit (MMU) manager. The protection service module is arranged to receive at least one virtual address and a first size information sent by a client of the APP. The primary VM includes a protection manager, and the protection manager is arranged to obtain a physical address array and a second size information according to the at least one virtual address and the first size information sent by the protection service through the hypervisor.
STORAGE SYSTEM WITH PASSIVE WITNESS NODE
A method for use in a first storage array, comprising: detecting whether a second storage array has designated the first storage array as a locally-preferred storage array, the detecting being performed when a first link between the second storage array and a witness node is down; setting a value of a first configuration setting to indicate that the first storage array is designated as a system-preferred storage array, the value of the first configuration setting being stored in a memory of the first storage array, the value of the first configuration setting being set only when the second storage array has designated the first storage array as a locally-preferred storage array; detecting, by the first storage array; and when the second link is down, assuming one of an active role or a passive role based, at least in part, on the value of the first configuration setting.
ACTIVE-PASSIVE CONFIGRATION FOR SYNCHRONOUS REMOTE REPLICATION IN AN ACTIVE-ACTIVE METRO CLUSTER
In one aspect, an example methodology implementing the disclosed techniques includes creating, by a first site of a volume that supports active-active bidirectional replication, a local copy of the volume, the local copy of the volume configured to be active. The method also includes enabling, by the first site of the volume, bidirectional write input/output (I/O) mirroring with a second site of the volume. The method further includes, by the second site of the volume, creating a remote copy of the volume, the remote copy of the volume configured to be passive, and enabling bidirectional write I/O mirroring with the first site of the volume.
Storage apparatus and control method of storage apparatus
A storage apparatus includes: a flash memory that provides a storage area; a controller that controls writing and reading of data to and from the storage area; and a buffer memory that temporarily stores data to be written in the storage area, in which the controller selects one compression method from a first reversible compression method and a second reversible compression method based on access performance to the flash memory, and determines to compress data based on the selected one compression method and to write the compressed data to the storage area, and the first reversible compression method has a lower compression ratio and a slower compression speed than the second reversible compression method.
SENSOR DEVICE
There is a possibility that unauthorized writing of adjustment information occurs in a sensor device in which the adjustment information of the sensor device can be written from outside. A sensor device 1 of the present embodiment includes a detection unit 2 configured to detect a physical quantity, a nonvolatile memory 5 configured to store adjustment information 6 and protection information 7, an adjustment unit 3 configured to adjust an output signal of the detection unit 2 based on contents of the adjustment information 6, an output unit 4 configured to output an output of the adjustment unit 3 to an outside via an external terminal 12, a communication unit 11 configured to communicate with the outside of the sensor device 1 via an external terminal 13, a writing unit 8 configured to perform writing process to the nonvolatile memory 6 based on information from the communication unit 11, an erasing unit 9 configured to perform erasing process of the nonvolatile memory 5 based on information from the communication unit 11, and a reading unit 10 configured to perform reading process from the nonvolatile memory 5 based on information from the communication unit 11.
RUNTIME NON-DESTRUCTIVE MEMORY BUILT-IN SELF-TEST (BIST)
Runtime memory BIST techniques are described herein. In one example, a system such as an SoC includes logic to schedule runtime testing of the memory that is non-destructive in multiple phases. Running testing of memory in multiple phases includes triggering a memory built-in self-test (BIST) testing of a subset of memory locations in a phase, where the processing logic is to pause access to the memory during the phase. The processing logic can resume access to the memory between testing phases. The next region of the memory can be tested in the phase that follows. This process can continue until the entire memory is tested, without requiring the system to be powered down.