An integrated circuit (IC) memory device encapsulated within an IC package. The memory device includes first memory regions configured to store lists of operands; a second memory region configured to store a list of results generated from the lists of operands; and at least one third memory region. A communication interface of the memory device can receive requests from an external processing device; and an arithmetic compute element matrix can access memory regions of the memory device in parallel. When the arithmetic compute element matrix is processing the lists of operands in the first memory regions and generating the list of results in the second memory region, the external processing device can simultaneously access the third memory region through the communication interface to load data into the third memory region, or retrieve results that have been previously generated by the arithmetic compute element matrix.

In certain aspects, a memory system includes a volatile memory device and a memory controller operatively coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller is configured to maintain the L2P mapping table stored in the volatile memory device, such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of memory blocks of a cache, respectively.

The information processing device acquires architecture model information including information representing communication paths for aggregating communication paths between ECU in a plurality of types of vehicles and data communication standards capable of transmitting and receiving data on respective communication paths, acquires variation information including information specifying necessary communication paths necessary for a particular vehicle and information specifying data necessary to be transmitted and received through a necessary communication path, generates a communication specification specifying a relationship between the necessary data and a communication path to which the necessary data should be transmitted based on the architecture model information and the variation information, and specifies a communication path for each necessary data, and specifies a communication path for each necessary data so as to satisfy a data communication standard defined for each necessary data when generating a communication specification.

Systems, apparatus, articles of manufacture, and methods are disclosed to implement memory sparing. An example memory controller includes first logic circuitry to: determine a first bank index for a bank of a memory that is to be moved; and determine if a first row index hash of an element in the bank of memory matches the first bank index; and second logic circuitry to: when the first row index hash matches the first bank index, move the element to a reserved row of the memory in the memory based on the first row index; and when the first row index hash does not match the first bank index, move the element to a bank in the reserved row that has a second bank index based on the first row index.

Generating a transformed dataset for use by a machine learning model in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (GPU) servers, including: storing, within one or more storage systems, a transformed dataset generated by applying one or more transformations to a dataset that are identified based on one or more expected input formats of data received as input data by one or more machine learning models to be executed on one or more servers; and transmitting, from the one or more storage systems to the one or more servers without reapplying the one or more transformations on the dataset, the transformed dataset including data in the one or more expected formats of data to be received as input data by the one or more machine learning models.

A storage system includes a plurality of drive nodes, a plurality of controller nodes controlling data from a host device to the plurality of drive nodes, and a processor that calculates long-term load fluctuation prediction as prediction of load fluctuation over a certain period of time in the future of the plurality of controller nodes based on time-series data of load of the plurality of controller nodes, and calculates an addition/reduction completion target time to complete addition or reduction of an operating controller node out of the plurality of controller nodes based on the long-term load fluctuation prediction and a load threshold value determined from a power performance model representing a relationship between the load and energy efficiency of the plurality of controller nodes.

Generating a transformed dataset for use by a machine learning model in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (GPU) servers, including: storing, within one or more storage systems, a transformed dataset generated by applying one or more transformations to a dataset that are identified based on one or more expected input formats of data received as input data by one or more machine learning models to be executed on one or more servers; and transmitting, from the one or more storage systems to the one or more servers without reapplying the one or more transformations on the dataset, the transformed dataset including data in the one or more expected formats of data to be received as input data by the one or more machine learning models.

Implementing a data movement network includes tiling one or more layers of a machine learning model based, at least in part, on amounts of addressable memory available in different memory levels of a memory architecture of an electronic system. Logical connections specifying compute tiles of the electronic system and logical address spaces corresponding to the compute tiles are generated. Physical connections are generated within the memory architecture by binding ports of direct memory access circuits of the memory architecture to the logical connections. Data transfers for memories between the different memory levels are scheduled based, at least in part, on a loop order of the tiling. Buffers for data of the data transfers are placed within the memories based on the scheduling.

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.