According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages first account information to be used for authentication of a first account and second account information to be used for authentication of a second account. The controller receives third account information from a host device. When the third account information matches the first account information, the controller permits access to at least a partial storage area of the nonvolatile memory based on a request from the host device and transmits first data that includes the second account information to a first memory system.

Verifying that data has been correctly replicated to a replication target, including: replicating a dataset stored at a first computing system to a second computing system; and determining, based at least on a comparison of a first hash and a second hash, validity of the dataset stored at the second computing system, wherein the first hash is generated by applying a hash function to a copy of the dataset that is stored at the first computing system and the second hash is generated by applying the hash function to a copy of the dataset that is stored at the second computing system.

An integrated circuit (IC) memory device encapsulated within an IC package. The memory device includes first memory regions configured to store lists of operands; a second memory region configured to store a list of results generated from the lists of operands; and at least one third memory region. A communication interface of the memory device can receive requests from an external processing device; and an arithmetic compute element matrix can access memory regions of the memory device in parallel. When the arithmetic compute element matrix is processing the lists of operands in the first memory regions and generating the list of results in the second memory region, the external processing device can simultaneously access the third memory region through the communication interface to load data into the third memory region, or retrieve results that have been previously generated by the arithmetic compute element matrix.

The present disclosure configures a system component, such as a memory sub-system controller, to provide notifications to a host system based on an single-level cell (SLC) storage tier. The controller stores data in a storage tier associated with a first type of storage. The controller determines an amount of space remaining in the storage tier for storing additional data and transmits a message to a host system representing the amount of space remaining in the storage tier for storing the additional data.

Methods, systems, and devices for redundant array parity information storage are described. A memory system may store parity information associated with data in one or more latches associated with one or more planes before writing the data from the latches to the one or more planes. The parity information may be transferred from the latches to the one or more planes. The memory system may temporarily transfer the parity information from the latches to the planes before completing the write operation in response to initiating a write operation that uses more of the latches, and may transfer the parity information back to the latches after the write operation is completed. The memory system may store, retrieve, and transfer the parity information to or from the latches according to an interleaving scheme associated with different write operations of the memory system.

Executing a machine learning model in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (GPU) servers, including: receiving, by a graphical processing unit (GPU) server, a dataset transformed by a storage system that is external to the GPU server; and executing, by the GPU server, one or more machine learning algorithms using the transformed dataset as input.

An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.

Memory defragmentation in a programmable integrated circuit (IC) device includes detecting, by computer hardware, instances of memory of a circuit design that are fragment memory instances. A group including a plurality of the fragment memory instances that are compatible with memory merger criteria are generated by the computer hardware. A composite memory is generated by the computer hardware by merging the fragment memory instances of the group. The fragment memory instances of the group are replaced with the composite memory.

Calculating storage consumption in a storage-as-a-service model, including: identifying a data object stored in a pool of storage resources, wherein the pool of storage resources are accessible by a plurality of entities and the data object occupies an amount of storage capacity within the pool of storage resources; attributing to each entity a fractional portion of the amount of storage capacity occupied by the data object; and calculating, in dependence upon the fractional portion of the amount of storage capacity occupied by the data object and attributed to a particular entity, a storage cost for the particular entity.

Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.