The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER). Each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

A system is provided including a first server storing a first data file for a first user, a second server storing a second data file for a second user, a first data card of the first user registered with the first server and locally storing a portion of the first data file, and a second data card of the second user registered with the second server and associated with the second data file. The first data card detects a pairing gesture between the first and second data cards, and in response, establishes a peer-to-peer connection between the data cards. The first data card subsequently detects a transfer gesture between the first and second data cards, and in response, transmits the portion of the first data file from the first data card to the second data card over the peer-to-peer connection.

An apparatus in one embodiment comprises at least one processing device configured to detect a plurality of asynchronous events in a storage system, wherein the storage system is configured to provide respective individual asynchronous event notifications for the detected asynchronous events to a host device in response to receipt of corresponding asynchronous event requests from the host device. The at least one processing device is further configured to determine that multiple ones of the asynchronous events have been detected in the storage system without receipt of respective ones of the corresponding asynchronous event requests from the host device, and to provide to the host device in response to a particular one of the asynchronous event requests received from the host device a summary notification comprising information indicative of the multiple detected asynchronous events. The at least one processing device illustratively comprises at least one storage controller of the storage system.

A DIMM (Dual In-line Memory Module) may include: one or more volatile memories, a nonvolatile memory having a first area where a reference parameter value which is expected to reduce the life expectancy of the volatile memory by a preset range or more, is stored and a second area where an excess counting value is stored, and a control circuit suitable for measuring an operation parameter value of the volatile memory, generating the excess counting value by counting the number of times that the operation parameter value exceeds the reference parameter value, and outputting the excess counting value stored in the second area to the outside through a preset pin in a preset operation mode.

A memory device, including a memory cell array including a plurality of memory cell rows; a monitoring cell array configured to detect a victim memory cell row of the plurality of memory cell rows, and to generate bit data; a bit data decoder configured to: receive the bit data, and based on the bit data, generate a victim memory address including address information about the victim memory cell row; and a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address

A semiconductor memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer handler configured to generate a refresh address when performing a refresh operation on the plurality rows of memory cells. The row hammer handler (RHH) includes a weight distributor configured to: receive a plurality of row addresses, assign a weight to each of the plurality of row addresses thus received, and to generate weight data corresponding to each of the plurality of row addresses. The RHH also includes an aggress address generator configured to determine an aggress address of a row of memory cells based on the weight data, and a refresh address generator configured to receive the aggress address and to generate the refresh address, which includes address information of a memory cell row adjacent the aggress address.

Various implementations described herein relate to systems and methods for predicting and managing drive hazards for Solid State Drive (SSD) devices in a data center, including receiving telemetry data corresponding to SSDs, determining future hazard of one of those SSDs based on an a-priori model or machine learning, and causing migration of data from that SSD to another SSD.

An improved information management system is described herein in which the information management system can evaluate the deduplication performance of secondary copy operations and dynamically adjust the manner in which secondary copy data is created to minimize the negative effects of performing deduplication. Furthermore, the improved information management system can improve deduplication performance by applying different storage policies to different types of applications running on a client computing device. Moreover, the improved information management system can automatically detect the region of a client computing device and apply an appropriate information management policy to the client computing device to avoid inconsistencies or other errors resulting from administrator control.

According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.

A common storage management device for a system including a common storage and at least one computer includes at least one processor, the at least one computer storing a plurality of applications configured to write and read data in the common storage. The at least one processor is configured to manage a reservation and a release of a storage space of the common storage in response to a request from the plurality of applications. The at least one processor is configured to assign a releasing priority to each storage space of the common storage that is reserved. The at least one processor is configured to instruct to release the storage space with highest releasing priority when the plurality of applications request to reserve the storage space for the data and free storage space is insufficient for reserving the storage space for the data.