To quickly and appropriately adjust a performance of a storage system. A storage configuration optimization device for managing a storage system including one or more storages implemented by a plurality of SDS nodes includes a virtual CPU. The virtual CPU is configured to receive a request for an execution period and a necessary performance of a project using the storage system, and select, based on consumption information and performance information of a resource of the storage system, one or more change patterns satisfying the request for the execution period and the necessary performance from among a plurality of change patterns indicating configuration changes of the storage system.

Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.

The disclosure provides an error detection method for a memory device, wherein the memory device comprises a plurality of memory blocks, and each of the memory blocks has a plurality of word lines connected to a plurality of memory cells, the error detection method comprises the following steps. Performing a plurality of times of programming operations on the memory cells connected to each of the word lines to program the memory cells as a plurality of programming-level states. Performing a plurality of times of verifying operations on the memory cells to verify the programming-level states respectively. When the number of verifications of the verifying operations for one of the programming-level states is greater than an upper limit number corresponding to the one of the programming-level states, marking the word line as an error word line.

A method for determining the memory power consumption includes: receiving a memory control command and controlling an analog memory to enter different working stages according to the memory control command (S410); acquiring an original current change curve of the analog memory in different working stages (S420); determining a target time period corresponding to a target working stage according to a time sequence of the memory control command (S430); intercepting a stage current change curve corresponding to the target working stage from the original current change curve according to the target time period to obtain a target current change curve (S440); selecting target performance parameters from a memory performance parameter table according to the target working stage (S450); and determining the power consumption of the memory according to the target performance parameters and the target current change curve (S460).

A storage device includes a memory and a memory controller which transmits a command to the memory. The memory includes at least one memory cell array, a memory temperature sensor which measures a temperature of the memory, and a control logic. The control logic outputs a busy signal in response to the command, receives the temperature of the memory from the memory temperature sensor in response to the command, and determines whether to perform a command operation according to the command on the memory cell array based on the received temperature of the memory.

An information handling system may include at least one processor; and a non-transitory memory coupled to the at least one processor. The information handling system may be configured to: receive health information for a plurality of node information handling systems; determine, based on the received health information, a score for each of the plurality of node information handling systems; determine an upgrade ordering for the plurality of node information handling systems based on the respective scores for the plurality of node information handling systems; and cause the node information handling systems to perform an upgrade procedure according to the upgrade ordering.

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

A method for managing overprovisioning in a solid state storage drive (SSD) array comprising (i) receiving usage data from each of a plurality of SSDs, (ii) determining a predicted service life value for each of the plurality of SSDs based on at least the usage data, (iii) comparing each of the predicted service life values with a predetermined service life value for each respective SSD, (iv) remapping at least one namespace in at least one of the plurality of SSDs among the plurality of SSDs, or reducing an available logical storage capacity for at least one of the plurality of SSDs. Here the remapping or reducing is based on a result of the comparing that the predicted service life value for the at least one of the plurality of SSDs is not greater than the predetermined service life value for that SSD.

A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

A solid state drive (SSD) is presented herein that includes a plurality of memory dies communicatively arranged in a plurality of communication channels such that each respective memory die is associated with a respective one communication channel of the plurality of communication channels, each respective memory die comprises one or more die regions, and each of the one or more die regions comprises a plurality of physical blocks configured to store data. The SSD further includes a memory controller communicatively coupled to the plurality of memory dies. The memory controller is configured to, upon a first power up of the SSD, determine a parameter of the SSD and for each of the one or more die regions, associate, based on the parameter, a number of physical blocks of the plurality of physical blocks with a block region of a plurality of block regions.