An information processing method, which is executed by a computer, includes detecting a first state in which an object is separated from an operation surface by a prescribed distance. detecting a second state in which the object comes in contact with the operation surface after the first state is detected. executing a first process which includes reading data from a first storage device and loading, into a second storage device, the data that are read, in response to the detecting of the first state, and executing a second process with respect to the data loaded into the second storage device, in response to the detecting of the second state.

A compilation method includes: receiving a signal to be compiled and a working frequency signal; performing compilation processing on the signal to be compiled to obtain a compilation result signal; and if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the working frequency signal to determine a first compilation value.

A processor is to execute a first instruction to perform a simulated return in a program from a callee function to a caller function based on a first input stack pointer encoded with a first security context of a first callee stack frame. To perform the simulated return is to include generating a first simulated stack pointer to the caller stack frame. The processor is further to, in response to identifying an exception handler in the first caller function, execute a second instruction to perform a simulated call based on a second input stack pointer encoded with a second security context of the caller stack frame. To perform the simulated call is to include generating a second simulated stack pointer to a new stack frame containing an encrypted instruction pointer associated with the exception handler. The second simulated stack pointer is to be encoded with a new security context.

Examples of scheduled and on-demand volume encryption suspension are described. A management service can identify multi-volume encryption rules for local volumes of a client device including the operating system volume as well as non-operating-system volumes. The encryption rules can be transmitted to the client device. Volume encryption samples for the client device can be received, and a console user interface can be generated to indicate compliance status information for the multi-volume encryption rules for local volumes of a client device.

An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.

Provided is a process that includes: obtaining a first request by a first program associated with a first sub-partition of a first partition of a tamper-evident data store of a decentralized computing platform to read data stored in either (i) a second sub-partition of the first partition of the tamper-evident data store of the decentralized computing platform, or (ii) a second partition of the tamper-evident data store of the decentralized computing platform; determining with a subset of peer computing nodes of a set of peer computing nodes that the first program is authorized to read from the second sub-partition or the second partition; and in response to the determination, causing the requested data to be read from the second sub-partition or the second partition.

A hardware-implemented, pre-sequence execution checker is used to receive a set of firmware instructions that includes a suspend command, an intervening command, and a resume command, wherein the suspend command and the resume command are associated with suspending and resuming a same command, respectively; access a configurable conditions table that includes whether the suspend command and the resume command are supported by a storage media device; access state information that includes whether said same command has completed; and determine whether to perform or skip the suspend command based at least in part on the configurable conditions table and the state information. If it is determined to perform the suspend command, the suspend command and the intervening command are output. If it is determined to skip the suspend command, the intervening command is output.

A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a first operation, corresponding to a first command, on the memory cell array. The control logic is configured to control the first operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to suspend the performance of the first operation and perform a second operation corresponding to a second command, in response to the second command being received while the first operation is being performed.