A communication circuit includes first and second communication nodes including first and second control chips, respectively, and first and second communication chips connected to the first and second control chips, respectively. The first and second communication chips are connected to each other through first and second signal lines, and are configured to transmit a differential signal. The first communication chip includes an output port to output a level signal obtained from the differential signal to the first control chip. The communication circuit further includes a voltage division assembly connected to the first and second signal lines, and configured to cause a voltage value of the first signal line to be higher than that of the second signal line when the first and second signal lines are in idle state. The first control chip includes a detection port connected to the output port to acquire the level signal.

A two-wire interface (300) for connecting a first device (106) and a second device (108). The two-wire interface (300) is operable in a handshaking mode and a data transfer mode. In the handshaking mode the first wire (302) of the interface (300) is driven by the first device (106) and the second wire (304) of the interface (300) is driven by the second device (108) so that the first (106) and second (108) devices can perform a handshaking sequence. In the data transfer mode one of the first wire (302) and the second wire (304) is driven by one of the first (106) and second (108) devices to provide a clock signal, and the other wire is driven by either the first device (106) or the second device (108) depending which device is transmitting data. Accordingly, the two-wire interfaces (300) are operable in two modes (e.g. handshaking mode and data transfer mode) and one of the wires (302, 304) of the interface (300) may be driven by a different device in the two modes.

Handshake controller and handshake control method for one or more charging protocols. For example, a handshake controller for one or more charging protocols includes: a port detection unit connected to a plurality of USB ports and configured to generate a detection signal; a port selection unit configured to receive the detection signal and connected to the plurality of USB ports; an interface unit connected to the port selection unit; and a digital handshake unit connected to the interface unit; wherein the port detection unit is further configured to: determine whether a single USB port of the plurality of USB ports is connected to a load device.

A method and an initiator device for autonomous detection of status of a link between the initiator device and a target device in a Universal Flash Storage (UFS) system. The method includes determining whether an Acknowledgement and Flow Control (AFC) frame for a data frame is received before expiry of a turn-around timer. If the AFC frame is received from the target device 200 before expiry of the turn-around timer, then the method detects the status of the link between the initiator device and the target device as active. If the AFC frame is not received from the target device before expiry of the turn-around timer then, the method detects the status of the link between the initiator device and the target device by restarting the turn-around timer with a second time period.

Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.

In one example, a communication device includes a LINK that generates a first output signal on a basis of a first external signal from a first external device, outputs the first output signal to a second external device, generates a second output signal on a basis of a second external signal from the second external device, and outputs the second output signal to the first external device, in which each of the first output signal and the second external signal includes command information indicating content of a command transmitted from the first external device, final-destination-device-identification-information for identifying a final destination device of data transmitted from the first external device, internal address information indicating an internal address of the final destination device, data length information indicating a length of the data transmitted from the first external device, and data-end-position-information indicating an end position of the data transmitted.

The invention relates to a method for implementing an industry internet field broadband bus, and in the method according to the invention, a bus controller and respective bus terminals transmit data in their respective time slices to thereby ensure timely and temporally determinist data transmission. Thus the embodiments of the invention implement a high-performance, highly reliable, and highly real-time method for implementing an industry internet field broadband bus. Moreover a transmission medium of the two-wire data transmission network can be a twisted pair or a shielded twisted pair so that the method according to the embodiment of the invention can be applicable to a traditional industry control facility using a bus, and thus can be highly universally applicable.

A functional node for an information transmission network and corresponding network are disclosed. In one aspect, the functional node includes at least one module for distributing messages between input and output ports. The distribution module includes at least one combination of at least three ports, including a first input port connected to a second output port by a first capability for unconditionally propagating messages, not depending on the messages. The first and/or second ports are connected to a third port by a second capability for conditionally propagating messages, depending on the messages.