Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.

Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.

A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

An Ethernet solid-state drive (eSSD) system includes a plurality of eSSDs, an Ethernet switch and a baseboard management controller. The Ethernet switch is coupled to each of the eSSDs, and the baseboard management controller is coupled to the each of the eSSDs and to the Ethernet switch. The baseboard management controller controls the Ethernet switch to provide to each eSSD a corresponding predetermined bandwidth that is based on bandwidth information for the eSSD that is stored in a policy table of the baseboard management controller. The at least one predetermined bandwidth may include a predetermined ingress bandwidth and a predetermined egress bandwidth for the corresponding eSSD. The at least one predetermined bandwidth may be based on a service level associated with the corresponding eSSD, and may be adaptively based on operating parameters of the corresponding eSSD.

Some embodiments relate to a link monitor for a switch having a PCIe-compliant interface. Some embodiments relate to an apparatus including a Peripheral Component Interconnect Express (PCIe)-compliant interface provided at a PCIe domain of a switch. The apparatus may also include a link monitor provided at a switching fabric of the switch that supports the PCIe domain of the switch. The link monitor to observe a factor-changing event of a state of a fabric link and obtain a value at least partially responsive to a weight computation, the weight computation for a factor associated with the factor-changing event. Related devices, systems and methods are also disclosed.

Techniques for transmitting data include identifying data to be transmitted, adding the data to a queue, and in response to a data session window being open: extracting the data from the queue; transmitting the extracted data to a transceiver via a transmitter; monitoring an amount of data in the queue and determining that the transmitter has transmitted the extracted data to the transceiver; and in response, instructing the transceiver to end the data session window early and transition to a lower power state.

According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

A serial communication apparatus capable of efficiently eliminating a timing lag between serial data transferred via a plurality of routes in serial communication is provided. The serial communication apparatus transfers serial data transmitted from a transmitting side communication unit disposed on a transmitting side to a receiving side communication unit disposed on a receiving side via a plurality of lanes. The transmitting side communication unit comprises a packet transmitting unit configured to divide transmission data into equal parts according to the number of the lanes, distribute the divided transmission data to each lane as a data main body, and add header information indicating the type of the transmission data to the divided transmission data distributed to each lane. The receiving side communication unit comprises a received packet skew adjusting unit configured to adjust skew of data received in each lane. The received packet skew adjusting unit detects the header information of the data received in each lane, writes the data main body of the received data to a data buffer at a detection timing, and starts data transfer from the data buffer to the outside at a timing when a writing access of the data main body of a predetermined number of cycles is completed in each lane.

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.