A Peripheral Component Interconnect Express (PCIe) data transmission method includes a first node that obtains a transaction layer packet (TLP). The TLP includes a TLP header, a TLP extension header, and data. The TLP header includes a type field, an Fmt field, and a reserved bit, and where the type field, the Fmt field, the reserved bit, and the TLP extension header indicate a data type of the data and at least one piece of attribute information corresponding to the data type such that, information, the data type and the at least one piece of the attribute information, to transmit the data is indicated using the type field, the Fmt field, the reserved bit, and the TLP extension header in the TLP.

A device charger with accessory bays is described. In some embodiments, an Information Handling System (IHS) may include: a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: receive an indication, from a device charger coupled to the IHS, that an accessory has been ejected from the device charger; and in response to the indication, connect to the accessory.

A KVM device supporting transmission of SuperSpeed USB signal and DisplayPort video signal is disclosed. The KVM device comprises a first USB Type-C connector, a first USB Type-C switch, a second USB Type-C connector, a second USB Type-C switch, a USB switch, a video switch, a control unit, a video connector, and at least one USB connector. When using this KVM device, the first USB Type-C connector and the second USB Type-C connector are electrically connected to a host electronic device through a first USB Type-C cable and a second USB Type-C cable, respectively. Therefore, the KVM device transmits DisplayPort video signal between the host computer and an external display device that is coupled to the video connector. Moreover, the KVM device also transmits SuperSpeed USB signal between the host computer and an external electronic device that is coupled to the USB connector.

A Peripheral Component Interconnect Express (PCIe)-based data transmission method includes a first node that encapsulates first data into a first transaction layer packet (TLP) and sends the first TLP to a second node, where a TLP header of the first TLP includes a first field, the first field is used to indicate a data type of the first data, and the data type includes at least one of the following: an image type, a video type, a control type, a security type, and a stream write (SWRITE) type. In embodiments of this application, the first field in the TLP header is used to indicate information required for data transmission, for example, the data type, so that nodes can communicate with each other without using a root complex.

A Peripheral Component Interconnect Express (PCIe)-based data transmission method includes that a first node obtains a transaction layer packet (TLP), where the TLP includes data, a type field, and at least one reserved bit, the type field and the at least one reserved bit indicate a first parameter set, and the first parameter set includes a data type of the data, and the first node sends the TLP to a second node.

A PCIe-based data transmission method and an apparatus are provided. The method includes the following: A first node obtains and sends a first TLP; and a switch receives the first TLP, and sends a second TLP to a second node. The first TLP includes a first TLP header and a first data payload, the second TLP includes a second TLP header and the first data payload, the first TLP header and the second TLP header are used to indicate a data type of the first data payload, and the data type of the first data payload includes at least one of audio, an image, control, data stream write, or security. The second node parses the first data payload based on the data type of the first data payload. This helps reduce communication complexity in a high-speed communication scenario.

In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.

A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller comprises configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are connected to the bus. Further, responsive to a determination by the arbitration logic that the multi-master controller controls the bus, the method comprises withdrawing the single master controller from attempting to control the bus.

A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.