An object is to reduce the number of writes of information managed by a controller to a non-volatile memory. A controller according to one aspect of the present invention includes: a first interface unit connected to a non-volatile memory including a plurality of blocks of memory cells that enter into both a first state and a second state and in which a plurality of addresses is allocated to the plurality of blocks; an information holding unit that holds first information; and a control unit that reads first data from a first block of the non-volatile memory via the first interface unit, specifies the memory cell in the second state among the memory cells in the first block and writes second data for causing the specified memory cell in the second state to transition to the first state, and selects one of the first information and the first data on the basis of the address of the first block and writes the selected first information or first data to the first block.

A device may include a buffer memory to buffer frames received or to be transmitted via a plurality of ports of the device. The device may include at least one frame processor to process frames. The device may include a buffer manager to store a frame in the buffer memory. The buffer manager may allocate at least one buffer control block (BCB) to the frame based on storing the frame in the buffer memory. The buffer manager may allocate a frame control block (FCB) to the frame. The FCB may include information that identifies the at least one BCB. The buffer manager may perform one or more queueing operations in association with processing of the frame by the at least one frame processor. The one or more queuing operations may be performed using information associated with the FCB.

A memory device includes an array of 2T1C DRAM cells and a memory controller. The DRAM cells are arranged as a plurality of rows and columns of DRAM cells. The memory controller is internal to the memory device and is coupled to the array of DRAM cells. The memory controller is capable of receiving commands input to the memory device and is responsive to the received commands to control row-major access and column-major access to the array of DRAM cells. In one embodiment, each transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor. In another embodiment, a first transistor of a memory cell includes a terminal directly coupled to a storage node of the capacitor, and a second transistor of the 2T1C memory cell includes a gate terminal directly coupled to the storage node of the capacitor.

According to one embodiment, a memory system is connectable to a host including a first volatile memory and includes a non-volatile memory and a controller. The controller may use a first area of the first volatile memory as a temporary storage memory of data stored in the non-volatile memory and controls the non-volatile memory. The controller generates a first parity by using first data stored in the non-volatile memory and a key value to store the first data and the generated first parity in the first area. In the case of reading the first data stored in the first area, the controller reads the first data and the first parity to verify the read first data using the read first parity and the key value.

A memory controller may calculate a sum of a first number of entries stored in a read buffer and a second number of entries stored in a write buffer. If the sum is less than a first threshold and the read/write buffer is not full of entries, then the memory controller can request read/write commands from a host computing device. If the sum is not less than the first threshold or the read/write buffer is full of entries, then the memory controller can assert backpressure to stop the incoming flow newly incoming read/write commands from the host computing device. Additionally, or alternatively, the memory controller may dequeue a write command entry only if a number of write command entries stored in a write command FIFO memory is greater than a second threshold. The memory controller may dequeue read command stored in a read FIFO memory if the number of write command entries stored in the write command FIFO memory is less than or equal to the second threshold and the read FIFO memory is not empty of the read command entries.

The present teaching relates to a method, system and programming for operating a data storage. The data storage comprises of different portions including: a first portion having a plurality of metadata objects stored therein, each of the metadata objects being associated with a filter and corresponding to a range of keys, wherein at least one of the metadata objects is associated with a data structure, and a second portion having a plurality of files stored therein, each of the plurality of files being associated with one of the plurality of metadata objects; The data storage synchronizes a scan request with respect to one or more write requests based on a parameter associated with the scan request and each of the one or more write requests.

Disclosed is a storage system comprising: receiving a first data segment and first metadata associated with the first data segment to be stored in the storage system; storing the first data segment and the first metadata in a persistent storage device of the storage system; compressing the first data segment using a predetermined compression algorithm to generate a first compressed data segment; and storing the first metadata and the first compressed data segment in a solid state drive (SSD) cache device of the storage system, including aligning the first metadata and the first compressed data segment to a page boundary of the SSD device to reduce a number of input and output (IO) operations required for accessing the first metadata and the first compressed data segment from the SSD cache device.

Disclosed is a memory system including a plurality of memory dies configured to store data in various storage modes; and a controller coupled with the plurality of memory dies via a plurality of channels and configured to perform a correlation operation on multiple read requests among a plurality of read requests received from a host so that the plurality of memory dies output plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way, wherein the controller is configured to determine whether to perform the correlation operation based on the number of read requests, and perform the correlation operation on the multiple read requests which are related to the same storage mode and different channels.

For restoring data, a system with uninterrupted block-based restore has a hybrid container. The hybrid container has an operational buffer and a virtual container unit. The system receives blocks of data from a target device into the hybrid container and sends the blocks of data from the hybrid container to a destination device for a restore session. The system writes information about the blocks of data into one or more virtual containers. If there is an abort of the restore session, the system freezes state of the hybrid container and the virtual container(s). For a next restore session that resumes from where the aborted restore session stopped, the system resumes receiving blocks of data from the target device into the hybrid container and sends only leftover blocks of data to the destination device in accordance with the information in the virtual container(s).

Disclosed are the SGL processing acceleration method and the storage device. The disclosed SGL processing acceleration method includes: obtaining the SGL associated with the IO command; generating the host space descriptor list and the DTU descriptor list according to the SGL; obtaining one or more host space descriptors of the host space descriptor list according to the DTU descriptor of the DTU descriptor list; and initiating the data transmission according to the obtained one or more host space descriptors.