A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

An array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. The array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. The array controller further comprises a control unit configured to enable a communication path between the solid state drive controller and one of the non-volatile storage units according to an address received from the solid state drive controller.

The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

A method for managing provenance information associated to one or more interconnected provenance entities in a provenance system for data processing pipelines in a distributed cloud environment over a network interface, wherein each of the data processing pipelines is configured to read in data, transform the data, and output transformed data is disclosed. The method comprises steps being performed by a configuration component of obtaining at least one declarative intent representing a configuration indicative of requirements and levels of priority for storage of provenance information for each of the data processing pipelines, deriving the requirements and levels of priority for storage of provenance information for each of the data processing pipelines based on the obtained at least one declarative intent, wherein one of the levels of priority—first level of priority—is higher than the other levels of priority—second levels of priority, estimating storage capacity for storage of provenance information in the provenance system based on the derived requirements and levels of priority, storing the provenance information according to the derived requirements and levels of priority for storage of provenance information and for each of the data processing pipelines, and when actual storage consumption for storage of provenance information in the provenance system meets a threshold of storage capacity set based on the estimated storage capacity: reducing a data amount for storage of provenance information of the second levels of priority in the provenance system. Corresponding computer program product, arrangement, configuration component, and system are also disclosed.

An edge accelerator card has a first interface, a second interface, a memory and a processor. The first interface is to couple to a server. The second interface is to couple to a storage system. The processor is to handle communication between the server and the storage system through the first interface and the second interface. The processor is to perform at least one task as directed by the storage system, using the memory and communication through at least the second interface.

Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.

The present disclosure discloses a control device of data storage system, including a host interface, a peer interface, a storage unit interface, a processor and a local data management module. The host interface is connected and communicated with a storage server for data interaction with the storage server. The peer interface is configured for data communication connection with a storage unit of an adjacent control device in the data storage system. The storage unit interface is configured to connect a storage unit. The local data management module is configured for local data management of the data in the storage unit according to the data management instruction via the processor. The host interface is configured to send result data of local data management to the storage server.

The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.